diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-27 13:39:12 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-06 16:13:49 +0000 |
| commit | f300f362103306775dab4fd994ca5e9fd59b96e4 (patch) | |
| tree | 166091b503338368b4b50dde5165903fbda64ac5 /src/northbridge | |
| parent | 485c0ad0783aa168feab8944e498a393774512fd (diff) | |
nb/intel/haswell: Use the common MRC cache driver
This driver uses an fmap region for the MRC cache instead of a CBFS
file which makes it easier to manage if one wants to write protect
it.
Change-Id: Iaa6b9f87c752088d70882fd05cb792e61a091391
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/Kconfig | 7 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/Makefile.inc | 12 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/raminit.c | 22 |
3 files changed, 13 insertions, 28 deletions
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index d5dec53041..5c8caea92d 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -16,7 +16,7 @@ config NORTHBRIDGE_INTEL_HASWELL bool select CPU_INTEL_HASWELL - select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE + select CACHE_MRC_SETTINGS select INTEL_DDI select INTEL_GMA_ACPI select RELOCATABLE_RAMSTAGE @@ -39,11 +39,6 @@ config CACHE_MRC_SIZE_KB int default 512 -config MRC_CACHE_SIZE - hex - depends on !CHROMEOS - default 0x10000 - config DCACHE_RAM_BASE hex default 0xff7c0000 diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index f198b7c027..c6d6b2eee8 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -36,16 +36,4 @@ mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) mrc.bin-position := 0xfffa0000 mrc.bin-type := mrc -ifneq ($(CONFIG_CHROMEOS),y) -$(obj)/mrc.cache: $(obj)/config.h - dd if=/dev/zero count=1 \ - bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \ - tr '\000' '\377' > $@ - -cbfs-files-y += mrc.cache -mrc.cache-file := $(obj)/mrc.cache -mrc.cache-align := 0x10000 -mrc.cache-type := mrc_cache -endif - endif diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index f17a374de4..e5e2b93cab 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -22,42 +22,44 @@ #include <halt.h> #include <ip_checksum.h> #include <memory_info.h> -#include <northbridge/intel/common/mrc_cache.h> +#include <mrc_cache.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> #include <device/dram/ddr3.h> #include <smbios.h> #include <spd.h> #include <security/vboot/vboot_common.h> +#include <commonlib/region.h> #include "raminit.h" #include "pei_data.h" #include "haswell.h" +#define MRC_CACHE_VERSION 1 + void save_mrc_data(struct pei_data *pei_data) { /* Save the MRC S3 restore data to cbmem */ - store_current_mrc_cache(pei_data->mrc_output, pei_data->mrc_output_len); + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, + pei_data->mrc_output, pei_data->mrc_output_len); } static void prepare_mrc_cache(struct pei_data *pei_data) { - struct mrc_data_container *mrc_cache; + struct region_device rdev; // preset just in case there is an error pei_data->mrc_input = NULL; pei_data->mrc_input_len = 0; - if ((mrc_cache = find_current_mrc_cache()) == NULL) { + if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev)) /* error message printed in find_current_mrc_cache */ return; - } - pei_data->mrc_input = mrc_cache->mrc_data; - pei_data->mrc_input_len = mrc_cache->mrc_data_size; + pei_data->mrc_input = rdev_mmap_full(&rdev); + pei_data->mrc_input_len = region_device_sz(&rdev); - printk(BIOS_DEBUG, "%s: at %p, size %x checksum %04x\n", - __func__, pei_data->mrc_input, - pei_data->mrc_input_len, mrc_cache->mrc_checksum); + printk(BIOS_DEBUG, "%s: at %p, size %x\n", + __func__, pei_data->mrc_input, pei_data->mrc_input_len); } static const char* ecc_decoder[] = { |