diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-09-10 20:36:14 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-12 14:41:54 +0000 |
| commit | e2983913373dd783f711b393e77682b8666283d1 (patch) | |
| tree | 1aab7394bd5b289f700b5790a92972df51ebf13a /src/northbridge | |
| parent | 08b5ef48346a0040d5d90b1fe1a9fd3e96b6a358 (diff) | |
nb/intel/i945/acpi: Convert i945.asl to ASL 2.0 syntax
It builds same binary for apple/macbook21 using BUILD_TIMELESS=1
Change-Id: I332afdcc4a1a7543571d8f9d121d8350347f7153
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45272
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/i945/acpi/i945.asl | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 789225ca71..cdc77b5fa7 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -8,13 +8,13 @@ Method (_OSC, 4) { /* Check for proper PCI/PCIe UUID */ - If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return(Arg3) } Else { CreateDWordField(Arg3, 0, CDW1) - Or(CDW1, 4, CDW1) // Unrecognized UUID, so set bit 2 to 1 + CDW1 = CDW1 | 4 // Unrecognized UUID, so set bit 2 to 1 Return(Arg3) } } @@ -52,22 +52,22 @@ Device (PDRC) Method (_CRS, 0, Serialized) { //CreateDwordField(PDRS, ^RCRB._BAS, RBR0) - //ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0) + //RBR0 = \_SB.PCI0.LPCB.RCBA << 14 //CreateDwordField(PDRS, ^MCHB._BAS, MBR0) - //ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0) + //MBR0 = \_SB.PCI0.MCHC.MHBR << 14 //CreateDwordField(PDRS, ^DMIB._BAS, DBR0) - //ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0) + //DBR0 = \_SB.PCI0.MCHC.DMBR << 12 //CreateDwordField(PDRS, ^EGPB._BAS, EBR0) - //ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0) + //EBR0 = \_SB.PCI0.MCHC.EPBR << 12 //CreateDwordField(PDRS, ^PCIE._BAS, PBR0) - //ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0) + //PBR0 = \_SB.PCI0.MCHC.PXBR << 26 //CreateDwordField(PDRS, ^PCIE._LEN, PSZ0) - //ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0) + //PSZ0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ Return(PDRS) } |