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authorMarshall Dawson <marshalldawson3rd@gmail.com>2019-06-20 10:29:29 -0600
committerMartin Roth <martinroth@google.com>2019-10-20 16:42:09 +0000
commitc0b8d0d5b5bd3f43e607ee317447d0a27fb5d474 (patch)
tree58f8e86bd3c5336c161b6caf57ecd530a4cd9684 /src/northbridge
parent0d441daef6e7ca4d43360058b960ccab8d2d21b5 (diff)
soc/amd/picasso: Update UARTs
Add a function to uart.c to ensure the right IOMux settings are programmed for the console UART. Update Kconfig to reflect the new addresses. Give the user the ability to downclock the UARTs' refclock to 1.8342MHz. Add the abiltiy to use an APU UART at a legacy I/O address. Update the AOAC register configuration for the two additional UARTs. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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