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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2018-07-25 15:27:50 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-07-25 14:20:22 +0000 |
| commit | b009ac49c85161ea2746f8bdfc6ce28a8f46e8bc (patch) | |
| tree | 12a528abc752666e57b9811e326dd099519f8dc7 /src/northbridge | |
| parent | 5ee9bc18407e4c2cad8e1c9e222ca16051d4b9b4 (diff) | |
nb/intel/sandybridge/raminit: Fix non ASCII char
Change-Id: I3f0869dc0b72bef7da8313c69da4fe2a63761ad9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27633
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 5cf9b69873..3e769ec5a4 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -265,7 +265,7 @@ void dram_timing_regs(ramctr_timing *ctrl) dram_odt_stretch(ctrl, channel); /* - * TC—Refresh timing parameters + * TC-Refresh timing parameters * The tREFIx9 field should be programmed to minimum of * 8.9*tREFI (to allow for possible delays from ZQ or * isoc) and tRASmax (70us) divided by 1024. |