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authorRonald G. Minnich <rminnich@gmail.com>2006-08-10 03:23:48 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-08-10 03:23:48 +0000
commitaf9cd4d0cf085a1b48e80b658841599b3831b8cd (patch)
tree07f79fed146a604342671d05758aa881e0fb5e68 /src/northbridge
parent08af3f535dd4446857e378b5dd87eb8ce35f823b (diff)
change from AMD for the IRQ10 problem.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2370 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/gx2/northbridge.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index 82175a5a66..1bb83868e3 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -276,11 +276,20 @@ static void enable_shadow(device_t dev)
static void northbridge_init(device_t dev)
{
+ unsigned long m;
+
struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
printk_debug("northbridge: %s()\n", __FUNCTION__);
enable_shadow(dev);
irq_init_steering(dev, nb->irqmap);
+
+ /* HACK HACK HACK HACK */
+ /* 0x1000 is where GPIO is being assigned */
+ m = inl(0x1038);
+ m &= ~GPIOL_12_SET;
+ m |= GPIOL_12_CLEAR;
+ outl(m, 0x1038);
}
/* due to vsa interactions, we need not not touch the nb settings ... */