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authorGreg Watson <jarrah@users.sourceforge.net>2004-06-05 14:36:23 +0000
committerGreg Watson <jarrah@users.sourceforge.net>2004-06-05 14:36:23 +0000
commit8ce104f487a8248be143b4436b7a4abc3969bb6f (patch)
tree25b52793e9be2be4b78a666f29e1d44e45722714 /src/northbridge
parent2f2e63bc7dd27b526d300a7aa712a0af4ec85e3e (diff)
memory and pci up!
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/ibm/cpc710/cpc710.c13
-rw-r--r--src/northbridge/ibm/cpc710/cpc710.h25
-rw-r--r--src/northbridge/ibm/cpc710/cpc710_pci.c133
-rw-r--r--src/northbridge/ibm/cpc710/cpc710_pci.h51
4 files changed, 112 insertions, 110 deletions
diff --git a/src/northbridge/ibm/cpc710/cpc710.c b/src/northbridge/ibm/cpc710/cpc710.c
index 3b96f51302..121ecef690 100644
--- a/src/northbridge/ibm/cpc710/cpc710.c
+++ b/src/northbridge/ibm/cpc710/cpc710.c
@@ -15,13 +15,13 @@ extern void cpc710_pci_init(void);
void
setCPC710(uint32_t addr, uint32_t data)
{
- out_be32((unsigned *)(CPC710_SCA_CPC0 + addr), data);
+ out_be32((unsigned *)(CPC710_PHYS_CPC0 + addr), data);
}
uint32_t
getCPC710(uint32_t addr)
{
- return (uint32_t)in_be32((unsigned *)(CPC710_SCA_CPC0 + addr));
+ return (uint32_t)in_be32((unsigned *)(CPC710_PHYS_CPC0 + addr));
}
void
@@ -34,6 +34,8 @@ sdram_init(void)
void
cpc710_init(void)
{
+ uint32_t mccr;
+
setCPC710(CPC710_CPC0_RSTR, 0xf0000000);
(void)getCPC710(CPC710_CPC0_MPSR);
setCPC710(CPC710_CPC0_SIOC0, 0x00000000);
@@ -74,4 +76,11 @@ cpc710_init(void)
setCPC710(CPC710_SDRAM0_MCER0, 0x80000080);
setCPC710(CPC710_SDRAM0_MCER1, 0x82000080);
setCPC710(CPC710_SDRAM0_MCCR, 0xd2b06000);
+
+ /*
+ * wait for SDRAM init
+ */
+ do {
+ mccr = getCPC710(CPC710_SDRAM0_MCCR);
+ } while (mccr & CPC710_MCCR_INIT_STATUS != CPC710_MCCR_INIT_STATUS);
}
diff --git a/src/northbridge/ibm/cpc710/cpc710.h b/src/northbridge/ibm/cpc710/cpc710.h
index f43a851cf2..7c5a37bb5c 100644
--- a/src/northbridge/ibm/cpc710/cpc710.h
+++ b/src/northbridge/ibm/cpc710/cpc710.h
@@ -81,35 +81,12 @@
#define CPC710_SDRAM0_SIOR0 0x1400
#define CPC710_SDRAM0_SIOR1 0x1420
-#define CPC710_BRIDGE_PSEA 0xf6110
-#define CPC710_BRIDGE_PCIDG 0xf6120
-#define CPC710_BRIDGE_INTACK 0xf7700
-#define CPC710_BRIDGE_PIBAR 0xf7800
-#define CPC710_BRIDGE_PMBAR 0xf7810
-#define CPC710_BRIDGE_CRR 0xf7ef0
-#define CPC710_BRIDGE_PR 0xf7f20
-#define CPC710_BRIDGE_ACR 0xf7f30
-#define CPC710_BRIDGE_MSIZE 0xf7f40
-#define CPC710_BRIDGE_IOSIZE 0xf7f60
-#define CPC710_BRIDGE_SMBAR 0xf7f80
-#define CPC710_BRIDGE_SIBAR 0xf7fc0
-#define CPC710_BRIDGE_CTLRW 0xf7fd0
-#define CPC710_BRIDGE_CFGADDR 0xf8000
-#define CPC710_BRIDGE_CFGDATA 0xf8010
-#define CPC710_BRIDGE_PSSIZE 0xf8100
-#define CPC710_BRIDGE_BARPS 0xf8120
-#define CPC710_BRIDGE_PSBAR 0xf8140
-#define CPC710_BRIDGE_BPMDLK 0xf8200
-#define CPC710_BRIDGE_TPMDLK 0xf8210
-#define CPC710_BRIDGE_BIODLK 0xf8220
-#define CPC710_BRIDGE_TIODLK 0xf8230
-#define CPC710_BRIDGE_INTSET 0xf8310
-
/* Configuration space registers */
#define CPC710_BUS_NUMBER 0x40
#define CPC710_SUB_BUS_NUMBER 0x41
/* MCCR register bits */
+#define CPC710_MCCR_INIT_STATUS 0x20000000
#define CPC710_MCCR_DIAG_MODE 0x40000000
#define CPC710_MCCR_ECC_DISABLE 0x08000000
#define CPC710_MCCR_REFRESH_7CY 0x02000000
diff --git a/src/northbridge/ibm/cpc710/cpc710_pci.c b/src/northbridge/ibm/cpc710/cpc710_pci.c
index 0083ae6480..b9820e5ab3 100644
--- a/src/northbridge/ibm/cpc710/cpc710_pci.c
+++ b/src/northbridge/ibm/cpc710/cpc710_pci.c
@@ -6,113 +6,112 @@
extern void setCPC710(uint32_t, uint32_t);
void
-setCPC710PCI32_16(uint32_t addr, uint16_t data)
+setCPC710_PCI32(uint32_t addr, uint32_t data)
{
- out_le16((unsigned short *)(CPC710_BRIDGE_CPCI_PHYS + addr), data);
+ out_be32((unsigned *)(CPC710_PCI32_CONFIG + addr), data);
}
+#if 0
void
-setCPC710PCI32_32(uint32_t addr, uint32_t data)
+setCPC710_PCI64(uint32_t addr, uint32_t data)
{
- out_le32((unsigned *)(CPC710_BRIDGE_CPCI_PHYS + addr), data);
-}
-
-void
-setCPC710PCI64_16(uint16_t addr, uint16_t data)
-{
- out_le16((unsigned short *)(CPC710_BRIDGE_LOCAL_PHYS + addr), data);
-}
-
-void
-setCPC710PCI64_32(uint32_t addr, uint32_t data)
-{
- out_le32((unsigned *)(CPC710_BRIDGE_LOCAL_PHYS + addr), data);
+ out_be32((unsigned *)(CPC710_PCI64_CONFIG + addr), data);
}
+#endif
void
cpc710_pci_init(void)
{
/* Enable PCI32 */
setCPC710(CPC710_CPC0_PCICNFR, 0x80000002); /* activate PCI32 config */
- setCPC710(CPC710_CPC0_PCIBAR, CPC710_BRIDGE_CPCI_PHYS); /* PCI32 base address */
+ setCPC710(CPC710_CPC0_PCIBAR, CPC710_PCI32_CONFIG); /* PCI32 base address */
setCPC710(CPC710_CPC0_PCIENB, 0x80000000); /* enable addr space */
setCPC710(CPC710_CPC0_PCICNFR, 0x00000000); /* config done */
/* Reset PCI Status register */
- setCPC710PCI32_32(CPC710_BRIDGE_CFGADDR, 0x80000006);
- setCPC710PCI32_16(CPC710_BRIDGE_CFGDATA, 0xffff);
+ pci_ppc_write_config16(0, 0, 0x06, 0xffff);
/* Configure bus number */
- setCPC710PCI32_32(CPC710_BRIDGE_CFGADDR, 0x80000040);
- setCPC710PCI32_16(CPC710_BRIDGE_CFGDATA, 0x0000);
+ pci_ppc_write_config16(0, 0, 0x40, 0);
/* Set PCI configuration registers */
- setCPC710PCI32_32(CPC710_BRIDGE_PCIDG, 0x40000000);
- setCPC710PCI32_32(CPC710_BRIDGE_PIBAR, 0x00000000);
- setCPC710PCI32_32(CPC710_BRIDGE_PMBAR, 0x00000000);
- setCPC710PCI32_32(CPC710_BRIDGE_PR, 0xa000c000);
- setCPC710PCI32_32(CPC710_BRIDGE_ACR, 0xfc000000);
- setCPC710PCI32_32(CPC710_BRIDGE_MSIZE, 0xf8000000); /* 128Mb */
- setCPC710PCI32_32(CPC710_BRIDGE_IOSIZE, 0xf8000000); /* 128Mb */
- setCPC710PCI32_32(CPC710_BRIDGE_SMBAR, 0xc0000000);
- setCPC710PCI32_32(CPC710_BRIDGE_SIBAR, 0x80000000);
- setCPC710PCI32_32(CPC710_BRIDGE_CTLRW, 0x00000000);
- setCPC710PCI32_32(CPC710_BRIDGE_PSSIZE, 0x00000080);
- setCPC710PCI32_32(CPC710_BRIDGE_BARPS, 0x00000000);
- setCPC710PCI32_32(CPC710_BRIDGE_PSBAR, 0x00000080);
- setCPC710PCI32_32(CPC710_BRIDGE_BPMDLK, 0x00000000);
- setCPC710PCI32_32(CPC710_BRIDGE_TPMDLK, 0x00000000);
- setCPC710PCI32_32(CPC710_BRIDGE_BIODLK, 0x00000000);
- setCPC710PCI32_32(CPC710_BRIDGE_TIODLK, 0x00000000);
+ setCPC710_PCI32(CPC710_PCIL0_PCIDG, 0x40000000);
+ setCPC710_PCI32(CPC710_PCIL0_PIBAR, 0x00000000);
+ setCPC710_PCI32(CPC710_PCIL0_PMBAR, 0x00000000);
+ setCPC710_PCI32(CPC710_PCIL0_PR, 0xa000c000);
+ setCPC710_PCI32(CPC710_PCIL0_ACR, 0xfc000000);
+ setCPC710_PCI32(CPC710_PCIL0_MSIZE, CPC710_PCI32_MEM_SIZE);
+ setCPC710_PCI32(CPC710_PCIL0_IOSIZE, CPC710_PCI32_IO_SIZE);
+ setCPC710_PCI32(CPC710_PCIL0_SMBAR, CPC710_PCI32_MEM_BASE);
+ setCPC710_PCI32(CPC710_PCIL0_SIBAR, CPC710_PCI32_IO_BASE);
+ setCPC710_PCI32(CPC710_PCIL0_CTLRW, 0x00000000);
+ setCPC710_PCI32(CPC710_PCIL0_PSSIZE, 0x00000080);
+ setCPC710_PCI32(CPC710_PCIL0_BARPS, 0x00000000);
+ setCPC710_PCI32(CPC710_PCIL0_PSBAR, 0x00000080);
+ setCPC710_PCI32(CPC710_PCIL0_BPMDLK, 0x00000000);
+ setCPC710_PCI32(CPC710_PCIL0_TPMDLK, 0x00000000);
+ setCPC710_PCI32(CPC710_PCIL0_BIODLK, 0x00000000);
+ setCPC710_PCI32(CPC710_PCIL0_TIODLK, 0x00000000);
/* Enable address space */
- setCPC710PCI32_32(CPC710_BRIDGE_CFGADDR, 0x80000004);
- setCPC710PCI32_16(CPC710_BRIDGE_CFGDATA, 0xfda7);
+ pci_ppc_write_config16(0, 0, 0x04, 0xfda7);
- setCPC710PCI32_32(CPC710_BRIDGE_CRR, 0xfc000000);
+ setCPC710_PCI32(CPC710_PCIL0_CRR, 0xfc000000);
+ /*
+ * wait for PCI to reset
+ */
+ udelay(250);
+
+#if 0
/* Enable PCI64 */
setCPC710(CPC710_CPC0_PCICNFR, 0x80000003); /* activate PCI64 config */
- setCPC710(CPC710_CPC0_PCIBAR, CPC710_BRIDGE_LOCAL_PHYS); /* PCI64 base address */
+ setCPC710(CPC710_CPC0_PCIBAR, CPC710_PCI64_CONFIG); /* PCI64 base address */
setCPC710(CPC710_CPC0_PCIENB, 0x80000000); /* enable addr space */
setCPC710(CPC710_CPC0_PCICNFR, 0x00000000); /* config done */
/* Reset PCI Status register */
- setCPC710PCI64_32(CPC710_BRIDGE_CFGADDR, 0x80000006);
- setCPC710PCI64_16(CPC710_BRIDGE_CFGDATA, 0xffff);
+ setCPC710_PCI64(CPC710_PCIL0_CFGADDR, 0x06000080);
+ setCPC710_PCI64_16(CPC710_PCIL0_CFGDATA, 0xffff);
/* Reset G_INT[A-D] bits in INT_RESET */
- setCPC710PCI64_32(CPC710_BRIDGE_CFGADDR, 0x80000068);
- setCPC710PCI64_32(CPC710_BRIDGE_CFGDATA, 0x0000000f);
+ setCPC710_PCI64(CPC710_PCIL0_CFGADDR, 0x68000080);
+ setCPC710_PCI64(CPC710_PCIL0_CFGDATA, 0x0f000000);
/* Configure bus number BUSNO=1, SUBNO=1 */
- setCPC710PCI64_32(CPC710_BRIDGE_CFGADDR, 0x80000040);
- setCPC710PCI64_16(CPC710_BRIDGE_CFGDATA, 0x0101);
+ setCPC710_PCI64(CPC710_PCIL0_CFGADDR, 0x40000080);
+ setCPC710_PCI64_16(CPC710_PCIL0_CFGDATA, 0x0101);
/* Set PCI configuration registers */
- setCPC710PCI64_32(CPC710_BRIDGE_PSEA, 0x00000000);
- setCPC710PCI64_32(CPC710_BRIDGE_PCIDG, 0xc0000000);
- setCPC710PCI64_32(CPC710_BRIDGE_PIBAR, 0x00000000);
- setCPC710PCI64_32(CPC710_BRIDGE_PMBAR, 0x00000000);
- setCPC710PCI64_32(CPC710_BRIDGE_PR, 0x80008000);
- setCPC710PCI64_32(CPC710_BRIDGE_ACR, 0xff000000);
- setCPC710PCI64_32(CPC710_BRIDGE_MSIZE, 0xf8000000); /* 128Mb */
- setCPC710PCI64_32(CPC710_BRIDGE_IOSIZE, 0xf8000000); /* 128Mb */
- setCPC710PCI64_32(CPC710_BRIDGE_SMBAR, 0xc8000000);
- setCPC710PCI64_32(CPC710_BRIDGE_SIBAR, 0x88000000);
- setCPC710PCI64_32(CPC710_BRIDGE_CTLRW, 0x02000000);
- setCPC710PCI64_32(CPC710_BRIDGE_PSSIZE, 0x00000080);
+ setCPC710_PCI64(CPC710_PCIL0_PSEA, 0x00000000);
+ setCPC710_PCI64(CPC710_PCIL0_PCIDG, 0xc0000000);
+ setCPC710_PCI64(CPC710_PCIL0_PIBAR, 0x00000000);
+ setCPC710_PCI64(CPC710_PCIL0_PMBAR, 0x00000000);
+ setCPC710_PCI64(CPC710_PCIL0_PR, 0x80008000);
+ setCPC710_PCI64(CPC710_PCIL0_ACR, 0xff000000);
+ setCPC710_PCI64(CPC710_PCIL0_MSIZE, CPC710_PCI64_MEM_SIZE);
+ setCPC710_PCI64(CPC710_PCIL0_IOSIZE, CPC710_PCI64_IO_SIZE);
+ setCPC710_PCI64(CPC710_PCIL0_SMBAR, CPC710_PCI64_MEM_BASE);
+ setCPC710_PCI64(CPC710_PCIL0_SIBAR, CPC710_PCI64_IO_BASE);
+ setCPC710_PCI64(CPC710_PCIL0_CTLRW, 0x02000000);
+ setCPC710_PCI64(CPC710_PCIL0_PSSIZE, 0x00000080);
/* Config PSBAR for PCI64 */
- setCPC710PCI64_32(CPC710_BRIDGE_CFGADDR, 0x80000010);
- setCPC710PCI64_32(CPC710_BRIDGE_CFGDATA, 0x80000000);
+ setCPC710_PCI64(CPC710_PCIL0_CFGADDR, 0x10000080);
+ setCPC710_PCI64(CPC710_PCIL0_CFGDATA, 0x00000080);
- setCPC710PCI64_32(CPC710_BRIDGE_BARPS, 0x00000000);
- setCPC710PCI64_32(CPC710_BRIDGE_INTSET, 0x00000000);
+ setCPC710_PCI64(CPC710_PCIL0_BARPS, 0x00000000);
+ setCPC710_PCI64(CPC710_PCIL0_INTSET, 0x00000000);
/* Enable address space */
- setCPC710PCI64_32(CPC710_BRIDGE_CFGADDR, 0x80010004);
- setCPC710PCI64_16(CPC710_BRIDGE_CFGDATA, 0xfda7);
+ setCPC710_PCI64(CPC710_PCIL0_CFGADDR, 0x04000180);
+ setCPC710_PCI64_16(CPC710_PCIL0_CFGDATA, 0xfda7);
+
+ setCPC710_PCI64(CPC710_PCIL0_CRR, 0xfc000000);
- setCPC710PCI64_32(CPC710_BRIDGE_CRR, 0xfc000000);
+ /*
+ * wait for PCI to reset
+ */
+ udelay(250);
+#endif
}
diff --git a/src/northbridge/ibm/cpc710/cpc710_pci.h b/src/northbridge/ibm/cpc710/cpc710_pci.h
index e2e12f21f3..a859ce374f 100644
--- a/src/northbridge/ibm/cpc710/cpc710_pci.h
+++ b/src/northbridge/ibm/cpc710/cpc710_pci.h
@@ -24,24 +24,41 @@
#ifndef _CPC710_PCI_H_
#define _CPC710_PCI_H_
-#define CPC710_PCI_MEMORY_PHYS 0x00000000
-#define CPC710_PCI_MEMORY_BUS 0x80000000
-#define CPC710_PCI_MEMORY_MAXSIZE 0x20000000
+#define CPC710_PCI32_CONFIG (PCIC0_CFGADDR & 0xfff00000)
+#define CPC710_PCI32_MEM_SIZE 0xf8000000
+#define CPC710_PCI32_MEM_BASE 0xc0000000
+#define CPC710_PCI32_IO_SIZE 0xf8000000
+#define CPC710_PCI32_IO_BASE 0x80000000
-#define CPC710_BRIDGE_CPCI_PHYS 0xff500000
-#define CPC710_BRIDGE_CPCI_MEM_SIZE 0x08000000
-#define CPC710_BRIDGE_CPCI_MEM_PHYS 0xf0000000
-#define CPC710_BRIDGE_CPCI_MEM_BUS 0x00000000
-#define CPC710_BRIDGE_CPCI_IO_SIZE 0x02000000
-#define CPC710_BRIDGE_CPCI_IO_PHY 0xfc000000
-#define CPC710_BRIDGE_CPCI_IO_BUS 0x00000000
+//#define CPC710_PCI64_CONFIG 0xff400000
+//#define CPC710_PCI64_MEM_SIZE 0xf8000000
+//#define CPC710_PCI64_MEM_BASE 0xc8000000
+//#define CPC710_PCI64_IO_SIZE 0xf8000000
+//#define CPC710_PCI64_IO_BASE 0x88000000
+
+#define CPC710_PCIL0_PSEA 0xf6110
+#define CPC710_PCIL0_PCIDG 0xf6120
+#define CPC710_PCIL0_INTACK 0xf7700
+#define CPC710_PCIL0_PIBAR 0xf7800
+#define CPC710_PCIL0_PMBAR 0xf7810
+#define CPC710_PCIL0_CRR 0xf7ef0
+#define CPC710_PCIL0_PR 0xf7f20
+#define CPC710_PCIL0_ACR 0xf7f30
+#define CPC710_PCIL0_MSIZE 0xf7f40
+#define CPC710_PCIL0_IOSIZE 0xf7f60
+#define CPC710_PCIL0_SMBAR 0xf7f80
+#define CPC710_PCIL0_SIBAR 0xf7fc0
+#define CPC710_PCIL0_CTLRW 0xf7fd0
+#define CPC710_PCIL0_CFGADDR 0xf8000 /* little endian */
+#define CPC710_PCIL0_CFGDATA 0xf8010 /* little endian */
+#define CPC710_PCIL0_PSSIZE 0xf8100
+#define CPC710_PCIL0_BARPS 0xf8120
+#define CPC710_PCIL0_PSBAR 0xf8140
+#define CPC710_PCIL0_BPMDLK 0xf8200
+#define CPC710_PCIL0_TPMDLK 0xf8210
+#define CPC710_PCIL0_BIODLK 0xf8220
+#define CPC710_PCIL0_TIODLK 0xf8230
+#define CPC710_PCIL0_INTSET 0xf8310
-#define CPC710_BRIDGE_LOCAL_PHYS 0xff400000
-#define CPC710_BRIDGE_LOCAL_MEM_SIZE 0x04000000
-#define CPC710_BRIDGE_LOCAL_MEM_PHYS 0xf8000000
-#define CPC710_BRIDGE_LOCAL_MEM_BUS 0x40000000
-#define CPC710_BRIDGE_LOCAL_IO_SIZE 0x01000000
-#define CPC710_BRIDGE_LOCAL_IO_PHYS 0xfe000000
-#define CPC710_BRIDGE_LOCAL_IO_BUS 0x04000000
#endif