cpu/mtrr.h: Fix macro names for MTRR registers

We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR,
we also remove the _MSR suffix, as they are, by definition, MSRs.

Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

3 files changed, 12 insertions, 12 deletions

diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 609cddf913..59a5fefd4b 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -1634,13 +1634,13 @@ static void set_var_mtrr_dqs(
 		zero.lo = zero.hi = 0;
 		/* The invalid bit is kept in the mask, so we simply clear the
 		   relevant mask register to disable a range. */
-		wrmsr (MTRRphysMask_MSR(reg), zero);
+		wrmsr (MTRR_PHYS_MASK(reg), zero);
 	} else {
 		/* Bit 32-35 of MTRRphysMask should be set to 1 */
 		base.lo |= type;
 		mask.lo |= 0x800;
-		wrmsr (MTRRphysBase_MSR(reg), base);
-		wrmsr (MTRRphysMask_MSR(reg), mask);
+		wrmsr (MTRR_PHYS_BASE(reg), base);
+		wrmsr (MTRR_PHYS_MASK(reg), mask);
 	}
 }
 
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index fc715bc1de..b48328f1b7 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -986,10 +986,10 @@ static inline void __attribute__((always_inline))
 		 */
 
 		/* Disable and invalidate all cache. */
-		msr_t xip_mtrr = rdmsr(MTRRphysMask_MSR(1));
-		xip_mtrr.lo &= ~MTRRphysMaskValid;
+		msr_t xip_mtrr = rdmsr(MTRR_PHYS_MASK(1));
+		xip_mtrr.lo &= ~MTRR_PHYS_MASK_VALID;
 		invd();
-		wrmsr(MTRRphysMask_MSR(1), xip_mtrr);
+		wrmsr(MTRR_PHYS_MASK(1), xip_mtrr);
 		invd();
 
 		RAM_DEBUG_MESSAGE("ECC state initialized.\n");
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index c41310a69a..232a15a239 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -2066,8 +2066,8 @@ static void disable_cache(void)
 {
 	msr_t msr = {.lo = 0, .hi = 0 };
 
-	wrmsr(MTRRphysBase_MSR(3), msr);
-	wrmsr(MTRRphysMask_MSR(3), msr);
+	wrmsr(MTRR_PHYS_BASE(3), msr);
+	wrmsr(MTRR_PHYS_MASK(3), msr);
 }
 
 static void enable_cache(unsigned int base, unsigned int size)
@@ -2075,11 +2075,11 @@ static void enable_cache(unsigned int base, unsigned int size)
 	msr_t msr;
 	msr.lo = base | MTRR_TYPE_WRPROT;
 	msr.hi = 0;
-	wrmsr(MTRRphysBase_MSR(3), msr);
-	msr.lo = ((~(ALIGN_DOWN(size + 4096, 4096) - 1) | MTRRdefTypeEn)
+	wrmsr(MTRR_PHYS_BASE(3), msr);
+	msr.lo = ((~(ALIGN_DOWN(size + 4096, 4096) - 1) | MTRR_DEF_TYPE_EN)
 		  & 0xffffffff);
 	msr.hi = 0x0000000f;
-	wrmsr(MTRRphysMask_MSR(3), msr);
+	wrmsr(MTRR_PHYS_MASK(3), msr);
 }
 
 static void flush_cache(u32 start, u32 size)
@@ -4017,7 +4017,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
 
 	write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) & 0xfc);
 #if !REAL
-	rdmsr (MTRRphysMask_MSR (3));
+	rdmsr (MTRR_PHYS_MASK (3));
 #endif
 
 	collect_system_info(&info);