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authorXavi Drudis Ferran <xdrudis@tinet.cat>2011-02-28 03:56:52 +0000
committerMarc Jones <marc.jones@amd.com>2011-02-28 03:56:52 +0000
commit6bdc83bf5e76aa0b36cb5f52c11544091d71770b (patch)
tree474451adb296e64baca29784ddf7bc87653b50d7 /src/northbridge
parent061c89e15d336b92b1e9fb2f9866c32f6496fb09 (diff)
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. I don't understand what this was doing nor find docs for these regs Maybe it was left over from some copy & paste ? Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/amdht/AsPsDefs.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h
index 6f03be886d..566e1fbbb0 100644
--- a/src/northbridge/amd/amdht/AsPsDefs.h
+++ b/src/northbridge/amd/amdht/AsPsDefs.h
@@ -58,7 +58,6 @@
#define PS_NB_VID_SHFT 25 /* P-state bit shift for NbVid */
#define PS_BOTH_VID_OFF 0x01ff01ff /* Mask NbVid & CpuVid */
#define PS_CPU_NB_VID_SHFT 16 /* P-state bit shift from CpuVid to NbVid */
-#define PS_NB_VID_SHFT 25 /* P-state NBVID shift */
#define PS_DIS 0x7fffffff /* disable P-state reg */
#define PS_EN 0x80000000 /* enable P-state reg */
#define PS_CPU_FID_MASK 0x03f /* MSRC001_00[68:64][CpuFid]