AMD fam10: Always have AMDMCT

Also drop some more #if UNUSED_CODE.

Change-Id: I1bbe96a65c9240636ff7cfaf70c2ecbfb3aee715
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8551
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

4 files changed, 2 insertions, 565 deletions

diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
index 8e1c4f8d5f..ff7fb9c17f 100644
--- a/src/northbridge/amd/amdfam10/Kconfig
+++ b/src/northbridge/amd/amdfam10/Kconfig
@@ -33,10 +33,6 @@ config AGP_APERTURE_SIZE
 	hex
 	default 0x4000000
 
-config AMDMCT
-	bool
-	default y
-
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index ab4b42e868..96f182da30 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -976,41 +976,10 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
 
 #include "raminit.h"
 
-#if !CONFIG_AMDMCT
-
-//struct definitions
-
-struct dimm_size {
-	u8 per_rank; // it is rows + col + bank_lines + data lines */
-	u8 rows;
-	u8 col;
-	u8 bank; //1, 2, 3 mean 2, 4, 8
-	u8 rank;
-} __attribute__((packed));
-
-struct mem_info { // pernode
-	u32 dimm_mask;
-	struct dimm_size sz[DIMM_SOCKETS*2]; // for ungang support
-	u32 x4_mask;
-	u32 x16_mask;
-	u32 single_rank_mask;
-	u32 page_1k_mask;
-//	  u32 ecc_mask;
-//	  u32 registered_mask;
-	u8 is_opteron;
-	u8 is_registered; //don't support mixing on the same channel or between channel
-	u8 is_ecc; //don't support mixing on the same channel or between channel
-	u8 is_Width128;
-	u8 memclk_set; // we need to use this to retrieve the mem param, all dimms need to work at same freq for one node
-	u8 is_cs_interleaved[2]; //cs
-	u8 rsv[1];
-} __attribute__((packed));
-#else
- #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
   #include "../amdmct/mct_ddr3/mct_d.h"
- #else
+#else
   #include "../amdmct/mct/mct_d.h"
- #endif
 #endif
 
 struct link_pair_t {
@@ -1034,13 +1003,6 @@ struct nodes_info_t {
 } __attribute__((packed));
 
 /* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and ramstage stage. and ramstage may be running at 64bit later.*/
-#if !CONFIG_AMDMCT
-
-//#define MEM_CS_COPY 1
-#define MEM_CS_COPY NODE_NUMS
-#define DQS_DELAY_COPY NODE_NUMS
-#endif
-
 
 struct sys_info {
 	int32_t needs_reset;
@@ -1066,29 +1028,8 @@ struct sys_info {
 
 	struct mem_controller ctrl[NODE_NUMS];
 
-#if CONFIG_AMDMCT
-//	sMCTStruct MCTData;
-//	sDCTStruct *DCTNodeData[NODE_NUMS];
-//	sDCTStruct DCTNodeData_a[NODE_NUMS];
 	struct MCTStatStruc MCTstat;
 	struct DCTStatStruc DCTstatA[NODE_NUMS];
-#else
-
-	u8 ctrl_present[NODE_NUMS];
-	struct mem_info meminfo[NODE_NUMS];
-	u8 mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail
-	u32 tom_m;
-	u32 tom2_m;
-
-	//if we are getting tight of global space, may need to squesh following to one copy
-	u32 mem_base[MEM_CS_COPY][2]; // two dct
-	u32 cs_base[MEM_CS_COPY][2][8]; //8 cs_idx
-	u32 hole_startk; // 0 mean hole
-
-	u8 dqs_delay_a[DQS_DELAY_COPY*2*4*2*9]; //8 node, channel 2, dimm 4, direction 2 , bytelane *9
-	u8 dqs_rcvr_dly_a[DQS_DELAY_COPY*2*4*9]; //8 node, channel 2, dimm 4, bytelane *9
-	u8 dqs_rcvr_dly_a_1[9]; //8 node, channel 2, dimm 4, bytelane *9
-#endif
 
 } __attribute__((packed));
 
@@ -1100,78 +1041,6 @@ extern struct sys_info sysinfo_car;
 device_t get_node_pci(u32 nodeid, u32 fn);
 #endif
 
-#if !CONFIG_AMDMCT
-
-#ifdef __PRE_RAM__
-static void soft_reset(void);
-#endif
-static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
-{
-	int i;
-	u32 mask_lo = 0;
-	u32 mask_hi = 0;
-	unsigned needs_reset = 0;
-
-	if(sysinfo->nodes == 1) return; // in case only one cpu installed
-		for(i=1; i<sysinfo->nodes; i++) {
-			/* Skip everything if I don't have any memory on this controller */
-			if(sysinfo->mem_trained[i]==0x00) continue;
-
-			if(i<32) {
-				mask_lo |= (1<<i);
-			} else {
-				mask_hi |= (1<<(i-32));
-			}
-	}
-
-	i = 1;
-	while(1) {
-		if(i<32) {
-			if(mask_lo & (1<<i)) {
-				if(sysinfo->mem_trained[i] != 0x80) {
-					mask_lo &= ~(1<<i);
-				}
-			}
-		} else {
-			if(mask_hi & (1<<(i-32))) {
-				if(sysinfo->mem_trained[i] != 0x80) {
-					 mask_hi &= ~(1<<(i-32));
-				}
-			}
-		}
-
-			if((!mask_lo) && (!mask_hi)) break;
-
-		i++;
-		i%=sysinfo->nodes;
-	}
-
-	for(i=0; i<sysinfo->nodes; i++) {
-		printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
-		switch(sysinfo->mem_trained[i]) {
-		case 0: //don't need train
-		case 1: //trained
-			break;
-		case 0x81: //recv1: fail
-		case 0x82: //Pos :fail
-		case 0x83: //recv2: fail
-			needs_reset = 1;
-			break;
-		}
-	}
-	if(needs_reset) {
-		printk(BIOS_DEBUG, "mem trained failed\n");
-#ifdef __PRE_RAM__
-		soft_reset();
-#else
-		hard_reset();
-#endif
-	}
-
-}
-
-#endif
-
 #ifdef __PRE_RAM__
 void showallroutes(int level, device_t dev);
 
diff --git a/src/northbridge/amd/amdfam10/conf.c b/src/northbridge/amd/amdfam10/conf.c
index 6688e0addb..9db685bef9 100644
--- a/src/northbridge/amd/amdfam10/conf.c
+++ b/src/northbridge/amd/amdfam10/conf.c
@@ -53,246 +53,6 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
 	return d;
 }
 
-#if !CONFIG_AMDMCT
-static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
-{
-	u32 i;
-	device_t dev;
-	u32 d_base_lo, d_base_hi, d_mask_lo, d_mask_hi;
-	u32 d_base_lo_reg, d_base_hi_reg, d_mask_lo_reg, d_mask_hi_reg;
-	d_mask_lo =  (((d.mask<<(8+3))|(0x07<<16)) & 0xffff0000)|nodeid; // need to fill DramMask[26:24] with ones
-	d_mask_hi =  (d.mask>>21) & 0xff;
-	d_base_lo = ((d.base<<(8+3)) & 0xffff0000);
-	if (d.mask & 1) d_base_lo |= 3;
-	d_base_hi = (d.base>>21) & 0xff;
-	d_mask_lo_reg = 0x44+(nodeid<<3);
-	d_mask_hi_reg = 0x144+(nodeid<<3);
-	d_base_lo_reg = 0x40+(nodeid<<3);
-	d_base_hi_reg = 0x140+(nodeid<<3);
-
-	for (i=0;i<nodes;i++) {
-#if defined(__PRE_RAM__)
-		dev = NODE_PCI(i, 1);
-#else
-		dev = __f1_dev[i];
-#endif
-		pci_write_config32(dev, d_mask_lo_reg, d_mask_lo); // need to fill DramMask[26:24] with ones
-		pci_write_config32(dev, d_mask_hi_reg, d_mask_hi);
-		pci_write_config32(dev, d_base_lo_reg, d_base_lo);
-		pci_write_config32(dev, d_base_hi_reg, d_base_hi);
-	}
-
-#if defined(__PRE_RAM__)
-	dev = NODE_PCI(nodeid, 1);
-#else
-	dev = __f1_dev[nodeid];
-#endif
-	pci_write_config32(dev, 0x120, d.base>>8);
-	pci_write_config32(dev, 0x124, d.mask>>8);
-
-}
-#endif
-
-#if !CONFIG_AMDMCT
-static void set_DctSelBaseAddr(u32 i, u32 sel_m)
-{
-	device_t dev;
-#if defined(__PRE_RAM__)
-	dev = NODE_PCI(i, 2);
-#else
-		dev = __f2_dev[i];
-#endif
-	u32 dcs_lo;
-	dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW);
-	dcs_lo &= ~(DCSL_DctSelBaseAddr_47_27_MASK<<DCSL_DctSelBaseAddr_47_27_SHIFT);
-	dcs_lo |= (sel_m<<(20+DCSL_DctSelBaseAddr_47_27_SHIFT-27));
-	pci_write_config32(dev, DRAM_CTRL_SEL_LOW, dcs_lo);
-
-}
-
-
-static u32 get_DctSelBaseAddr(u32 i)
-{
-	device_t dev;
-#if defined(__PRE_RAM__)
-	dev = NODE_PCI(i, 2);
-#else
-		dev = __f2_dev[i];
-#endif
-	u32 sel_m;
-	u32 dcs_lo;
-	dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW);
-	dcs_lo &= DCSL_DctSelBaseAddr_47_27_MASK<<DCSL_DctSelBaseAddr_47_27_SHIFT;
-	sel_m = dcs_lo>>(20+DCSL_DctSelBaseAddr_47_27_SHIFT-27);
-	return sel_m;
-}
-
-#ifdef UNUSED_CODE
-static void set_DctSelHiEn(u32 i, u32 val)
-{
-	device_t dev;
-#if defined(__PRE_RAM__)
-	dev = NODE_PCI(i, 2);
-#else
-		dev = __f2_dev[i];
-#endif
-	u32 dcs_lo;
-	dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW);
-	dcs_lo &= ~(7);
-	dcs_lo |= (val & 7);
-	pci_write_config32(dev, DRAM_CTRL_SEL_LOW, dcs_lo);
-
-}
-#endif
-
-static u32 get_DctSelHiEn(u32 i)
-{
-	device_t dev;
-#if defined(__PRE_RAM__)
-	dev = NODE_PCI(i, 2);
-#else
-	dev = __f2_dev[i];
-#endif
-	u32 dcs_lo;
-	dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW);
-	dcs_lo &= 7;
-	return dcs_lo;
-
-}
-
-static void set_DctSelBaseOffset(u32 i, u32 sel_off_m)
-{
-	device_t dev;
-#if defined(__PRE_RAM__)
-	dev = NODE_PCI(i, 2);
-#else
-	dev = __f2_dev[i];
-#endif
-	u32 dcs_hi;
-	dcs_hi = pci_read_config32(dev, DRAM_CTRL_SEL_HIGH);
-	dcs_hi &= ~(DCSH_DctSelBaseOffset_47_26_MASK<<DCSH_DctSelBaseOffset_47_26_SHIFT);
-	dcs_hi |= sel_off_m<<(20+DCSH_DctSelBaseOffset_47_26_SHIFT-26);
-	pci_write_config32(dev, DRAM_CTRL_SEL_HIGH, dcs_hi);
-
-}
-
-#ifdef UNUSED_CODE
-static u32 get_DctSelBaseOffset(u32 i)
-{
-	device_t dev;
-#if defined(__PRE_RAM__)
-	dev = NODE_PCI(i, 2);
-#else
-	dev = __f2_dev[i];
-#endif
-	u32 sel_off_m;
-	u32 dcs_hi;
-	dcs_hi = pci_read_config32(dev, DRAM_CTRL_SEL_HIGH);
-	dcs_hi &= DCSH_DctSelBaseOffset_47_26_MASK<<DCSH_DctSelBaseOffset_47_26_SHIFT;
-	sel_off_m = dcs_hi>>(20+DCSH_DctSelBaseOffset_47_26_SHIFT-26);
-	return sel_off_m;
-}
-#endif
-
-static u32 get_one_DCT(struct mem_info *meminfo)
-{
-	u32 one_DCT = 1;
-	if (meminfo->is_Width128) {
-		one_DCT = 1;
-	} else {
-		u32 dimm_mask = meminfo->dimm_mask;
-		if ((dimm_mask >> DIMM_SOCKETS) && (dimm_mask & ((1<<DIMM_SOCKETS)-1))) {
-			 one_DCT = 0;
-		}
-	}
-
-	return one_DCT;
-}
-
-#if CONFIG_HW_MEM_HOLE_SIZEK != 0
-// See that other copy in northbridge.c
-static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes)
-{
-	u32 ii;
-	u32 carry_over;
-	device_t dev;
-	struct dram_base_mask_t d;
-	u32 sel_m;
-	u32 sel_hi_en;
-	u32 hoist;
-
-
-	carry_over = (4*1024*1024) - hole_startk;
-
-	for (ii=nodes - 1;ii>i;ii--) {
-		d = get_dram_base_mask(ii);
-		if (!(d.mask & 1)) continue;
-		d.base += (carry_over>>9);
-		d.mask += (carry_over>>9);
-		set_dram_base_mask(ii, d, nodes);
-
-		if (get_DctSelHiEn(ii) & 1) {
-			sel_m = get_DctSelBaseAddr(ii);
-			sel_m += carry_over>>10;
-			set_DctSelBaseAddr(ii, sel_m);
-		}
-
-	}
-	d = get_dram_base_mask(i);
-	d.mask += (carry_over>>9);
-	set_dram_base_mask(i,d, nodes);
-#if defined(__PRE_RAM__)
-	dev = NODE_PCI(i, 1);
-#else
-	dev = __f1_dev[i];
-#endif
-	sel_hi_en =  get_DctSelHiEn(i);
-	if (sel_hi_en & 1) {
-		sel_m = get_DctSelBaseAddr(i);
-	}
-	if (d.base == (hole_startk>>9)) {
-		//don't need set memhole here, because hole off set will be 0, overflow
-		//so need to change base reg instead, new basek will be 4*1024*1024
-		d.base = (4*1024*1024)>>9;
-		set_dram_base_mask(i, d, nodes);
-
-		if (sel_hi_en & 1) {
-			sel_m += carry_over>>10;
-			set_DctSelBaseAddr(i, sel_m);
-		}
-	} else {
-		hoist = /* hole start address */
-			((hole_startk << 10) & 0xff000000) +
-			/* enable */
-			1;
-		if (one_DCT||(sel_m>=(hole_startk>>10))) { //one DCT or hole in DCT0
-			hoist +=
-			/* hole address to memory controller address */
-			((((d.base<<9) + carry_over) >> 6) & 0x0000ff00) ;
-
-			if (sel_hi_en & 1) {
-				sel_m += (carry_over>>10);
-				set_DctSelBaseAddr(i, sel_m);
-				set_DctSelBaseOffset(i, sel_m);
-			}
-		} else { // hole in DCT1 range
-			hoist +=
-			/* hole address to memory controller address */
-			((((sel_m<<10) + carry_over) >> 6) & 0x0000ff00) ;
-			// don't need to update DctSelBaseAddr
-			if (sel_hi_en & 1) {
-				set_DctSelBaseOffset(i, sel_m);
-			}
-		}
-		pci_write_config32(dev, 0xf0, hoist);
-
-	}
-
-	return carry_over;
-}
-#endif
-#endif // CONFIG_AMDMCT
-
 
 static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
 				u32 busn_min, u32 busn_max, u32 segbit,
@@ -402,43 +162,6 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
 }
 #endif
 
-#ifdef UNUSED_CODE
-static void re_set_all_config_map_reg(u32 nodes, u32 segbit,
-					sys_info_conf_t *sysinfo)
-{
-	u32 ht_c_index;
-	device_t dev;
-
-	set_config_map_reg(0, sysinfo->sblk, 0, 0, sysinfo->ht_c_conf_bus[0]>>20, segbit, nodes);
-
-	/* clean others */
-	for (ht_c_index=1;ht_c_index<4; ht_c_index++) {
-		u32 i;
-		for (i=0; i<nodes; i++) {
-		#if defined(__PRE_RAM__)
-			dev = NODE_PCI(i, 1);
-		#else
-			dev = __f1_dev[i];
-		#endif
-			pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
-		}
-	}
-
-	for (ht_c_index = 1; ht_c_index<sysinfo->ht_c_num; ht_c_index++) {
-		u32 nodeid, linkn;
-		u32 busn_max;
-		u32 busn_min;
-		nodeid = (sysinfo->ht_c_conf_bus[ht_c_index] >> 2) & 0x3f;
-		linkn = (sysinfo->ht_c_conf_bus[ht_c_index]>>8) & 0x7;
-		busn_max = sysinfo->ht_c_conf_bus[ht_c_index]>>20;
-		busn_min = (sysinfo->ht_c_conf_bus[ht_c_index]>>12) & 0xff;
-		busn_min |= busn_max & 0xf00;
-		set_config_map_reg(nodeid, linkn, ht_c_index, busn_min, busn_max, segbit, nodes);
-	}
-
-}
-#endif
-
 static u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo)
 {
 	u32 tempreg;
@@ -480,27 +203,6 @@ static void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index,
 
 }
 
-#ifdef UNUSED_CODE
-static  void set_BusSegmentEn(u32 node, u32 segbit)
-{
-#if CONFIG_PCI_BUS_SEGN_BITS
-	u32 dword;
-	device_t dev;
-
-#if defined(__PRE_RAM__)
-	dev = NODE_PCI(node, 0);
-#else
-	dev = __f0_dev[node];
-#endif
-
-	dword = pci_read_config32(dev, 0x68);
-	dword &= ~(7<<28);
-	dword |= (segbit<<28); /* bus segment enable */
-	pci_write_config32(dev, 0x68, dword);
-#endif
-}
-#endif
-
 #if !defined(__PRE_RAM__)
 static u32 get_io_addr_index(u32 nodeid, u32 linkn)
 {
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index f28c726875..cbeddf2aad 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -739,87 +739,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 		return mem_hole;
 }
 
-// WHY this check? CONFIG_AMDMCT is enabled on all Fam10 boards.
-// Does it make sense not to?
-#if !CONFIG_AMDMCT
-static void disable_hoist_memory(unsigned long hole_startk, int node_id)
-{
-	int i;
-	device_t dev;
-	struct dram_base_mask_t d;
-	u32 sel_m;
-	u32 sel_hi_en;
-	u32 hoist;
-	u32 hole_sizek;
-
-	u32 one_DCT;
-	struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM
-	struct mem_info *meminfo;
-	meminfo = &sysinfox->meminfo[node_id];
-
-	one_DCT = get_one_DCT(meminfo);
-
-	// 1. find which node has hole
-	// 2. change limit in that node.
-	// 3. change base and limit in later node
-	// 4. clear that node f0
-
-	// if there is not mem hole enabled, we need to change it's base instead
-
-	hole_sizek = (4*1024*1024) - hole_startk;
-
-	for(i=NODE_NUMS-1;i>node_id;i--) {
-
-		d = get_dram_base_mask(i);
-
-		if(!(d.mask & 1)) continue;
-
-		d.base -= (hole_sizek>>9);
-		d.mask -= (hole_sizek>>9);
-		set_dram_base_mask(i, d, sysconf.nodes);
-
-		if(get_DctSelHiEn(i) & 1) {
-			sel_m = get_DctSelBaseAddr(i);
-			sel_m -= hole_startk>>10;
-			set_DctSelBaseAddr(i, sel_m);
-		}
-	}
-
-	d = get_dram_base_mask(node_id);
-	dev = __f1_dev[node_id];
-	sel_hi_en = get_DctSelHiEn(node_id);
-
-	if(sel_hi_en & 1) {
-		sel_m = get_DctSelBaseAddr(node_id);
-	}
-	hoist = pci_read_config32(dev, 0xf0);
-	if(hoist & 1) {
-		pci_write_config32(dev, 0xf0, 0);
-		d.mask -= (hole_sizek>>9);
-		set_dram_base_mask(node_id, d, sysconf.nodes);
-		if(one_DCT || (sel_m >= (hole_startk>>10))) {
-			if(sel_hi_en & 1) {
-				sel_m -= hole_startk>>10;
-				set_DctSelBaseAddr(node_id, sel_m);
-			}
-		}
-		if(sel_hi_en & 1) {
-			set_DctSelBaseOffset(node_id, 0);
-		}
-	} else {
-		d.base -= (hole_sizek>>9);
-		d.mask -= (hole_sizek>>9);
-		set_dram_base_mask(node_id, d, sysconf.nodes);
-
-		if(sel_hi_en & 1) {
-			sel_m -= hole_startk>>10;
-			set_DctSelBaseAddr(node_id, sel_m);
-		}
-	}
-
-}
-#endif
-
 #endif
 
 #include <cbmem.h>
@@ -947,44 +866,6 @@ static void amdfam10_domain_set_resources(device_t dev)
 		reset_memhole = 0;
 	}
 
-	#if !CONFIG_AMDMCT
-	//mmio_basek = 3*1024*1024; // for debug to meet boundary
-
-	if(reset_memhole) {
-		if(mem_hole.node_id!=-1) {
-		/* We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not
-		    make hole_startk to some basek too!
-		   We need to reset our Mem Hole, because We want more big HOLE
-		    than we already set
-		   Before that We need to disable mem hole at first, becase
-		    memhole could already be set on i+1 instead
-		 */
-			disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
-		}
-
-	#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-		// We need to double check if the mmio_basek is valid for hole
-		// setting, if it is equal to basek, we need to decrease it some
-		resource_t basek_pri;
-		for (i = 0; i < sysconf.nodes; i++) {
-			struct dram_base_mask_t d;
-			resource_t basek;
-			d = get_dram_base_mask(i);
-
-			if(!(d.mask &1)) continue;
-
-			basek = ((resource_t)(d.base & 0x1fffff00)) << 9;
-			if(mmio_basek == (u32)basek) {
-				mmio_basek -= (uin32_t)(basek - basek_pri); // increase mem hole size to make sure it is on middle of pri node
-				break;
-			}
-			basek_pri = basek;
-		}
-	#endif
-	}
-	#endif
-
-
 #endif
 
 	idx = 0x10;
@@ -1021,17 +902,6 @@ static void amdfam10_domain_set_resources(device_t dev)
 					if (!ramtop)
 						ramtop = mmio_basek * 1024;
 				}
-				#if !CONFIG_AMDMCT
-				#if CONFIG_HW_MEM_HOLE_SIZEK != 0
-				if(reset_memhole) {
-					struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM
-					struct mem_info *meminfo;
-					meminfo = &sysinfox->meminfo[i];
-					sizek += hoist_memory(mmio_basek,i, get_one_DCT(meminfo), sysconf.nodes);
-				}
-				#endif
-				#endif
-
 				basek = mmio_basek;
 			}
 			if ((basek + sizek) <= 4*1024*1024) {