zero warnings days. Down to under 600 different warnings

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

12 files changed, 35 insertions, 44 deletions

diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c
index bb37481d10..be02ab3d3b 100644
--- a/src/northbridge/amd/amdht/h3finit.c
+++ b/src/northbridge/amd/amdht/h3finit.c
@@ -1692,7 +1692,7 @@ void tuning(sMainData *pDat)
  *	@param[out] result BOOL  = true if check is ok, false if it failed
  * ---------------------------------------------------------------------------------------
  */
-BOOL isSanityCheckOk()
+BOOL isSanityCheckOk(void)
 {
 	uint64 qValue;
 
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index 3f9e89d63c..190529ce04 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -123,9 +123,9 @@ struct msr_defaults {
 };
 
 /* note that dev is NOT used -- yet */
-static void irq_init_steering(struct device *dev, uint16_t irq_map) {
+static void irq_init_steering(struct device *dev, u16 irq_map) {
 	/* Set up IRQ steering */
-	uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
+	u32 pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
 
 	printk(BIOS_DEBUG, "%s(%p [%08X], %04X)\n", __func__, dev, pciAddr, irq_map);
 
@@ -298,17 +298,17 @@ static void northbridge_init(device_t dev)
 /* this is a test -- we are not sure it will work -- but it ought to */
 static void set_resources(struct device *dev)
 {
+#if 0
         struct resource *resource, *last;
-        unsigned link;
-        uint8_t line;
 
-#if 0
         last = &dev->resource[dev->resources];
 
         for(resource = &dev->resource[0]; resource < last; resource++) {
                 pci_set_resource(dev, resource);
         }
 #endif
+        unsigned link;
+
         for(link = 0; link < dev->links; link++) {
                 struct bus *bus;
                 bus = &dev->link[link];
@@ -327,7 +327,7 @@ static void set_resources(struct device *dev)
         }
 
         /* zero the irq settings */
-        line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
+        u8 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
         if (line) {
                 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
         }
@@ -383,10 +383,10 @@ static void tolm_test(void *gp, struct device *dev, struct resource *new)
 }
 
 #if 0
-static uint32_t find_pci_tolm(struct bus *bus)
+static u32 find_pci_tolm(struct bus *bus)
 {
 	struct resource *min;
-	uint32_t tolm;
+	u32 tolm;
 	min = 0;
 	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
 	tolm = 0xffffffffUL;
@@ -402,7 +402,7 @@ static void pci_domain_set_resources(device_t dev)
 {
 #if 0
 	device_t mc_dev;
-        uint32_t pci_tolm;
+        u32 pci_tolm;
 
         pci_tolm = find_pci_tolm(&dev->link[0]);
 	mc_dev = dev->link[0].children;
diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c
index 7d33e44236..5023edb546 100644
--- a/src/northbridge/via/vt8623/northbridge.c
+++ b/src/northbridge/via/vt8623/northbridge.c
@@ -60,7 +60,10 @@ static void northbridge_init(device_t dev)
 	}
 }
 
-static void nullfunc(){}
+static void nullfunc(void)
+{
+	/* Nothing to do */
+}
 
 static struct device_operations northbridge_operations = {
 	.read_resources   = nullfunc,
@@ -104,7 +107,7 @@ static const struct pci_driver agp_driver __pci_driver = {
 
 static void vga_init(device_t dev)
 {
-//	unsigned long fb;
+	//unsigned long fb;
 	//msr_t clocks1,clocks2,instructions,setup;
 
 	printk(BIOS_DEBUG, "VGA random fixup ...\n");
diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c
index 7ec3c86aef..3a29d29aca 100644
--- a/src/northbridge/via/vx800/dev_init.c
+++ b/src/northbridge/via/vx800/dev_init.c
@@ -26,7 +26,7 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr);
 void InitDDR2CHB(DRAM_SYS_ATTR *DramAttr);
 void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr);
 
-CB_STATUS VerifyChc();
+CB_STATUS VerifyChc(void);
 
 /*===================================================================
 Function   : DRAMRegInitValue()
diff --git a/src/northbridge/via/vx800/dram_init.c b/src/northbridge/via/vx800/dram_init.c
index d059b519ef..b6c8cf2ab0 100644
--- a/src/northbridge/via/vx800/dram_init.c
+++ b/src/northbridge/via/vx800/dram_init.c
@@ -17,12 +17,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-CB_STATUS DDR2_DRAM_INIT()
+CB_STATUS DDR2_DRAM_INIT(void)
 {
-	CB_STATUS Status;
 	u8 i;
 	u32 RamSize;
-	BOOLEAN bTest;
 	DRAM_SYS_ATTR DramAttr;
 
 	PRINT_DEBUG_MEM("DRAM_INIT \r");
@@ -76,7 +74,7 @@ CB_STATUS DDR2_DRAM_INIT()
 	PRINT_DEBUG_MEM_HEX32(RamSize);
 	PRINT_DEBUG_MEM("\r");
 	DumpRegisters(0, 3);
-	//bTest = DramBaseTest( M1, RamSize - M1 * 2,SPARE, FALSE);
+	//BOOLEAN bTest = DramBaseTest( M1, RamSize - M1 * 2,SPARE, FALSE);
 	/* the memory can not correct work, this is because the user set the incorrect memory
 	   parameter from setup interface.so we must set the boot mode to recovery mode, let
 	   the system to reset and use the spd value to initialize the memory */
diff --git a/src/northbridge/via/vx800/dram_init.h b/src/northbridge/via/vx800/dram_init.h
index 51b98934e5..27f73f0f4d 100644
--- a/src/northbridge/via/vx800/dram_init.h
+++ b/src/northbridge/via/vx800/dram_init.h
@@ -253,9 +253,9 @@ void DRAMRefreshCounter(DRAM_SYS_ATTR * DramAttr);
 void DRAMRegFinalValue(DRAM_SYS_ATTR * DramAttr);
 
 /*set UMA*/
-void SetUMARam();
+void SetUMARam(void);
 
 CB_STATUS InstallMemory(DRAM_SYS_ATTR * DramAttr, u32 RamSize);
-CB_STATUS DDR2_DRAM_INIT();
+CB_STATUS DDR2_DRAM_INIT(void);
 
 #endif
diff --git a/src/northbridge/via/vx800/drdy_bl.c b/src/northbridge/via/vx800/drdy_bl.c
index 627fb28552..da8aae13c8 100644
--- a/src/northbridge/via/vx800/drdy_bl.c
+++ b/src/northbridge/via/vx800/drdy_bl.c
@@ -407,9 +407,6 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr)
 	u8 Data, CL, RDRPH;
 	u8 CpuFreq, DramFreq;
 	u8 ProgData[PT894_RDRDY_TBL_Width];
-	u8 DelayMode;
-	u8 DrdyMode;
-	u8 Index;
 
 	/*
 	   this function has 3 switchs, correspond to 3 level of Drdy setting.
@@ -483,16 +480,19 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr)
 	Data = pci_read_config8(MEMCTRL, 0x90);
 	DramFreq = Data & 0x07;
 
+	u8 DelayMode;
 	DelayMode = CL + RDRPH;	// RDELAYMD = bit0 of (CAS Latency + RDRPH)
 	DelayMode &= 0x01;
 
 	//In 364, there is no 128 bit
 	if (DelayMode == 1) {	// DelayMode 1
+		u8 Index;
 		for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++)
 			ProgData[Index] =
 			    PT894_64bit_DELAYMD1_RCONV0[CpuFreq][DramFreq]
 			    [Index];
 	} else {		// DelayMode 0
+		u8 Index;
 		for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++)
 			ProgData[Index] =
 			    PT894_64bit_DELAYMD0_RCONV0[CpuFreq][DramFreq]
diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c
index b81b90de79..47a99c3cc1 100644
--- a/src/northbridge/via/vx800/freq_setting.c
+++ b/src/northbridge/via/vx800/freq_setting.c
@@ -120,7 +120,7 @@ static const u8 CL_DDR2[7] = { 0, 0, 20, 30, 40, 50, 60 };
 void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr)
 {
 	u8 AllDimmSupportedCL, Tmp;
-	u8 CLMask, tmpMask, IndexDelta;
+	u8 CLMask, tmpMask;
 	u8 SckId, BitId, TmpId;
 	u16 CycTime, TmpCycTime;
 
diff --git a/src/northbridge/via/vx800/raminit.c b/src/northbridge/via/vx800/raminit.c
index 4daf2b785d..ce9b7d4fab 100644
--- a/src/northbridge/via/vx800/raminit.c
+++ b/src/northbridge/via/vx800/raminit.c
@@ -55,9 +55,8 @@
  * Support one dimm with up to 2 ranks
  */
 
-static void ddr2_ram_setup()
+static void ddr2_ram_setup(void)
 {
-	u8 Data;
 	CB_STATUS Status;
 	PRINT_DEBUG_MEM("In ddr2_ram_setup\r");
 
diff --git a/src/northbridge/via/vx800/rank_map.c b/src/northbridge/via/vx800/rank_map.c
index 00e1e47fa3..df39ce5899 100644
--- a/src/northbridge/via/vx800/rank_map.c
+++ b/src/northbridge/via/vx800/rank_map.c
@@ -138,7 +138,6 @@ void DRAMSizingEachRank(DRAM_SYS_ATTR * DramAttr)
 	u32 Size;
 	BOOLEAN HasThreeBitBA;
 	u8 Data;
-	u32 Address;
 
 	HasThreeBitBA = FALSE;
 	for (Slot = 0; Slot < 2; Slot++) {
diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c
index 6988ffe4b0..71379e7ec3 100644
--- a/src/northbridge/via/vx800/uma_ram_setting.c
+++ b/src/northbridge/via/vx800/uma_ram_setting.c
@@ -333,6 +333,7 @@ void SetUMARam(void)
 	ByteVal = (ByteVal & 0xE5) | 0x1A;
 	outb(ByteVal, 0x03d5);
 
+#if 0
 	u8 table3c43c5[0x70] = {
 		0x03, 0x01, 0x0F, 0x00, 0x06, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -395,9 +396,9 @@ void SetUMARam(void)
 		0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 		0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 	};
-#if 0
-//for(i=0;i<0xc0;i++)
-	for (i = 0; i < 0x40; i++)	//
+
+	//for(i=0;i<0xc0;i++)
+	for (i = 0; i < 0x40; i++)
 	{
 		outb(table3c0space[i], 0x03c0 + i);
 	}
@@ -410,6 +411,7 @@ void SetUMARam(void)
 		outb(i, 0x03d4);
 		outb(table3d43d5[i], 0x03d5);
 	}
+
 	outb(0x92, 0x03d4);
 	outb(0x80, 0x03d5);
 
@@ -419,12 +421,12 @@ void SetUMARam(void)
 	outb(0xe8, 0x03d4);
 	outb(0x40, 0x03d5);
 #endif
-//3d4 3d freq
-//IO Port / Index: 3X5.3D
-//Scratch Pad Register 4
 
-//    outb(0x39,0x03c4);//
-	//outb(1 << SLD0F3Val ,0x03c5);
+// 3d4 3d freq
+// IO Port / Index: 3X5.3D
+// Scratch Pad Register 4
+//	outb(0x39,0x03c4);
+//	outb(1 << SLD0F3Val ,0x03c5);
 //
 #endif
 
diff --git a/src/northbridge/via/vx800/vgabios.c b/src/northbridge/via/vx800/vgabios.c
index f8029ae157..9690170d1e 100644
--- a/src/northbridge/via/vx800/vgabios.c
+++ b/src/northbridge/via/vx800/vgabios.c
@@ -299,8 +299,6 @@ void do_vgabios(void)
 	unsigned char *buf;
 	unsigned int size = 64 * 1024;
 	int i;
-	u16 tmp;
-	u8 tmp8;
 
 	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
@@ -646,15 +644,7 @@ pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
 	unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
 	unsigned long *pecx, unsigned long *peax, unsigned long *pflags)
 {
-	unsigned long edi = *pedi;
-	unsigned long esi = *pesi;
-	unsigned long ebp = *pebp;
-	unsigned long esp = *pesp;
-	unsigned long ebx = *pebx;
-	unsigned long edx = *pedx;
-	unsigned long ecx = *pecx;
 	unsigned long eax = *peax;
-	unsigned long flags = *pflags;
 	unsigned short func = (unsigned short)eax;
 	int retval = 0;
 	unsigned short devid, vendorid, devfn;