diff options
| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-10-26 10:36:02 +1100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2014-11-05 14:53:56 +0100 |
| commit | 3ec9c95d02e8c67fb05ad580b5ca7a1fd14d2b02 (patch) | |
| tree | a470484ac451b672181acec8ab77e3c0b80958fb /src/northbridge | |
| parent | 016732fec9e99cafd0b1b66c0e5214f0783580f0 (diff) | |
Use 'pci_devfn_t' over 'device_t' mixed type in 'reset.c'
Change-Id: I1a1412a1ee4125dcf1f01dc1f2ec6fd43b5d3c1f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7196
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdfam10/reset_test.c | 10 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/reset_test.c | 4 |
2 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index 24f5397631..de7949ef6a 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -32,7 +32,7 @@ u32 cpu_init_detected(u8 nodeid) { u32 htic; - device_t dev; + pci_devfn_t dev; dev = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(dev, HT_INIT_CONTROL); @@ -67,7 +67,7 @@ u32 other_reset_detected(void) // other warm reset not started by BIOS static void distinguish_cpu_resets(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; @@ -77,7 +77,7 @@ static void distinguish_cpu_resets(u8 nodeid) static u32 warm_reset_detect(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); @@ -89,7 +89,7 @@ void __attribute__ ((weak)) set_bios_reset(void) u32 nodes; u32 htic; - device_t dev; + pci_devfn_t dev; int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; @@ -134,7 +134,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b int i; int j; u32 cfg_map_dest; - device_t dev; + pci_devfn_t dev; cfg_map_dest = (1<<7)|(1<<6)|link; diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index 6ef3ec0c59..8015290250 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -10,7 +10,7 @@ static inline int cpu_init_detected(unsigned nodeid) { u32 htic; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); @@ -37,7 +37,7 @@ static inline int cold_reset_detected(void) static inline void distinguish_cpu_resets(unsigned nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; |