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authorAaron Durbin <adurbin@chromium.org>2012-11-29 17:21:51 -0600
committerRonald G. Minnich <rminnich@gmail.com>2013-03-14 05:08:02 +0100
commit30c3900451756793144bb579acc59205381138ab (patch)
tree2fae98a6a3e936c12abb5847d34ac23835da66a6 /src/northbridge
parent8256a9b715df14dc8914b641796344ac513cb889 (diff)
haswell: notes and updates.
Add a FIXME about checking a MCHBAR register that isn't setup yet. Also, remove revision updating because I can't find anything in the docs that suggest this is required for haswell. Change-Id: Ia8a6e08f82e18789e31c6c2ec2c1d63740c18dc4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2631 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/haswell/early_init.c15
1 files changed, 0 insertions, 15 deletions
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 4d174740f1..505fbf1125 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -139,21 +139,6 @@ static void haswell_setup_graphics(void)
void haswell_early_initialization(int chipset_type)
{
- u32 capid0_a;
- u8 reg8;
-
- /* Device ID Override Enable should be done very early */
- capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
- if (capid0_a & (1 << 10)) {
- reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3);
- reg8 &= ~7; /* Clear 2:0 */
-
- if (chipset_type == HASWELL_MOBILE)
- reg8 |= 1; /* Set bit 0 */
-
- pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8);
- }
-
/* Setup all BARs required for early PCIe and raminit */
haswell_setup_bars();