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authorRonald G. Minnich <rminnich@gmail.com>2006-08-09 02:21:49 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-08-09 02:21:49 +0000
commit08af3f535dd4446857e378b5dd87eb8ce35f823b (patch)
treef2b9bb3333d0f4f5ffeca8becee256f050e51e67 /src/northbridge
parente53d03c2113ea08e3b604341835504c49333b95b (diff)
mods for the ultra40 bringup. This now builds.
amd gx2 north -- don't set anything in the north, it conflicts with vsa settings. So we have our own pci_set_resources that is essentially a no-op -- just calls the kids. olpc rev_a config -- DISABLE the compressed rom stream. This SHOULD NOT have been set -- it is untested and caused real trouble. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/gx2/northbridge.c47
1 files changed, 47 insertions, 0 deletions
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index a0ad84669f..82175a5a66 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -283,9 +283,56 @@ static void northbridge_init(device_t dev)
irq_init_steering(dev, nb->irqmap);
}
+/* due to vsa interactions, we need not not touch the nb settings ... */
+/* this is a test -- we are not sure it will work -- but it ought to */
+static void set_resources(struct device *dev)
+{
+ struct resource *resource, *last;
+ unsigned link;
+ uint8_t line;
+
+#if 0
+ last = &dev->resource[dev->resources];
+
+ for(resource = &dev->resource[0]; resource < last; resource++) {
+ pci_set_resource(dev, resource);
+ }
+#endif
+ for(link = 0; link < dev->links; link++) {
+ struct bus *bus;
+ bus = &dev->link[link];
+ if (bus->children) {
+ assign_resources(bus);
+ }
+ }
+
+#if 0
+ /* set a default latency timer */
+ pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
+
+ /* set a default secondary latency timer */
+ if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
+ pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
+ }
+
+ /* zero the irq settings */
+ line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
+ if (line) {
+ pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
+ }
+ /* set the cache line size, so far 64 bytes is good for everyone */
+ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
+#endif
+}
+
+
+
static struct device_operations northbridge_operations = {
.read_resources = pci_dev_read_resources,
+#if 0
.set_resources = pci_dev_set_resources,
+#endif
+ .set_resources = set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
.enable = 0,