remove more warnings

rename amd64_main to stage1_main.. 
copy src/mainboard/via/vt8454c/debug.c to src/lib/debug.c

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 22 insertions, 19 deletions

diff --git a/src/northbridge/via/cx700/cx700_early_smbus.c b/src/northbridge/via/cx700/cx700_early_smbus.c
index 361b5e9bca..b1d6344f6d 100644
--- a/src/northbridge/via/cx700/cx700_early_smbus.c
+++ b/src/northbridge/via/cx700/cx700_early_smbus.c
@@ -57,6 +57,7 @@
 #endif
 
 /* Internal functions */
+#if CONFIG_DEBUG_SMBUS
 static void smbus_print_error(unsigned char host_status_register, int loops)
 {
 	/* Check if there actually was an error */
@@ -87,6 +88,7 @@ static void smbus_print_error(unsigned char host_status_register, int loops)
 		print_err("Host Busy\n");
 	}
 }
+#endif
 
 static void smbus_wait_until_ready(void)
 {
@@ -127,7 +129,7 @@ static void set_ics_data(unsigned char dev, int data, char len)
 	inb(SMBHSTCTL);
 
 	/* fill blocktransfer array */
-	if (dev = 0xd2) {
+	if (dev == 0xd2) {
 		//char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b};
 		outb(0x0d, SMBBLKDAT);
 		outb(0x00, SMBBLKDAT);
@@ -231,7 +233,7 @@ static void enable_smbus(void)
 }
 
 /* Debugging Function */
-#ifdef CONFIG_DEBUG_SMBUS
+#if CONFIG_DEBUG_SMBUS
 static void dump_spd_data(const struct mem_controller *ctrl)
 {
 	int dimm, offset, regs;
diff --git a/src/northbridge/via/cx700/cx700_lpc.c b/src/northbridge/via/cx700/cx700_lpc.c
index d6495aba61..02beb86283 100644
--- a/src/northbridge/via/cx700/cx700_lpc.c
+++ b/src/northbridge/via/cx700/cx700_lpc.c
@@ -84,7 +84,7 @@ static void pci_routing_fixup(struct device *dev)
  * can't figure out how to do !!!!
  */
 
-void setup_pm(device_t dev)
+static void setup_pm(device_t dev)
 {
 	/* Debounce LID and PWRBTN# Inputs for 16ms. */
 	pci_write_config8(dev, 0x80, 0x20);
@@ -236,7 +236,7 @@ static void cx700_set_lpc_registers(struct device *dev)
 
 }
 
-void cx700_read_resources(device_t dev)
+static void cx700_read_resources(device_t dev)
 {
 	struct resource *res;
 
@@ -258,7 +258,7 @@ void cx700_read_resources(device_t dev)
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
-void cx700_set_resources(device_t dev)
+static void cx700_set_resources(device_t dev)
 {
 	struct resource *resource;
 	resource = find_resource(dev, 1);
@@ -266,7 +266,7 @@ void cx700_set_resources(device_t dev)
 	pci_dev_set_resources(dev);
 }
 
-void cx700_enable_resources(device_t dev)
+static void cx700_enable_resources(device_t dev)
 {
 	/* Enable SuperIO decoding */
 	pci_dev_enable_resources(dev);
diff --git a/src/northbridge/via/cx700/cx700_reset.c b/src/northbridge/via/cx700/cx700_reset.c
index 80e09d7fab..83439881f6 100644
--- a/src/northbridge/via/cx700/cx700_reset.c
+++ b/src/northbridge/via/cx700/cx700_reset.c
@@ -18,6 +18,7 @@
  */
 
 #include <arch/io.h>
+#include <reset.h>
 
 void hard_reset(void)
 {
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index d28b8e37c4..d68ad3b2c2 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -103,15 +103,15 @@
 	} while ( 0 )
 
 #define REGISTERPRESET(bus,dev,fun,bdfspec) \
-	{ u8 i, reg; \
-		for (i=0; i<(sizeof((bdfspec))/sizeof(struct regmask)); i++) { \
+	{ u8 j, reg; \
+		for (j=0; j<(sizeof((bdfspec))/sizeof(struct regmask)); j++) { \
 			printk(BIOS_DEBUG, "Writing bus " #bus " dev " #dev " fun " #fun " register "); \
-			printk(BIOS_DEBUG, "%02x", (bdfspec)[i].reg); \
+			printk(BIOS_DEBUG, "%02x", (bdfspec)[j].reg); \
 			printk(BIOS_DEBUG, "\n"); \
-			reg = pci_read_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[i].reg); \
-			reg &= (bdfspec)[i].mask; \
-			reg |= (bdfspec)[i].val; \
-			pci_write_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[i].reg, reg); \
+			reg = pci_read_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[j].reg); \
+			reg &= (bdfspec)[j].mask; \
+			reg |= (bdfspec)[j].val; \
+			pci_write_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[j].reg, reg); \
 		} \
 	}
 
@@ -1436,23 +1436,23 @@ static void sdram_enable(const struct mem_controller *ctrl)
 		{ 0x67, ~0x03, 0x01},
 		{ 0x5b, ~0x01, 0x00},
 		{ 0x8d, ~0x02, 0x02},
-		{ 0x97, ~0x80, 0x00},
+		{ 0x97, 0x7f, 0x00},
 		{ 0xd2, ~0x18, 0x00},
 		{ 0xe2, ~0x36, 0x06},
-		{ 0xe4, ~0x80, 0x00},
+		{ 0xe4, 0x7f, 0x00},
 		{ 0xe5, 0x00, 0x40},
 		{ 0xe6, 0x00, 0x20},
-		{ 0xe7, ~0xd0, 0xc0},
+		{ 0xe7, 0x2f, 0xc0},
 		{ 0xec, ~0x08, 0x00}
 	}, b0d17f7[] = {
-		{ 0x4e, ~0x80, 0x80},
+		{ 0x4e, 0x7f, 0x80},
 		{ 0x4f, ~(1 << 6), 1 << 6 },	/* PG_CX700: 14.1.1 enable P2P Bridge Header for External PCI Bus */
 		{ 0x74, ~0x00, 0x04},		/* PG_CX700: 14.1.2 APIC FSB directly up to snmic, not on pci */
 		{ 0x7c, ~0x00, 0x02},		/* PG_CX700: 14.1.1 APIC FSB directly up to snmic, not on pci */
 		{ 0xe6, 0x0, 0x04}		// MSI post
 	}, b0d19f0[] = {	/* P2PE */
 		{ 0x42, ~0x08, 0x08},		// Disable HD Audio,
-		{ 0x40, ~0xc0, 0x80}		// 14.1.3.1.1 of the PG: extended cfg mode for pcie. enable capability, but don't activate
+		{ 0x40, 0x3f, 0x80}		// 14.1.3.1.1 of the PG: extended cfg mode for pcie. enable capability, but don't activate
 	}, b0d0f2[] = {
 		{ 0x50, ~0x40, 0x88},
 		{ 0x51, 0x80, 0x7b},
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index 22c0fbd40f..a9f22ac0f1 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -300,7 +300,7 @@ void EmbedComInit()
 
 /* cache_as_ram.inc jump to here
 */
-void amd64_main(unsigned long bist)
+void stage1_main(unsigned long bist)
 {
 	unsigned cpu_reset = 0;
 	u16 boot_mode;