northbridge: Drop print_ implementation from non-romcc boards

Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the northbridge code to use printk() on all non-ROMCC
boards.

Change-Id: I4a36cd965c58aae65d74ce1e697dc0d0f58f47a1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7856
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)

14 files changed, 99 insertions, 128 deletions

diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index 0103c4ff18..747cbfd922 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -25,10 +25,10 @@
 #include "cn700.h"
 
 #if CONFIG_DEBUG_RAM_SETUP
-#define PRINT_DEBUG_MEM(x)		print_debug(x)
-#define PRINT_DEBUG_MEM_HEX8(x)		print_debug_hex8(x)
-#define PRINT_DEBUG_MEM_HEX16(x)	print_debug_hex16(x)
-#define PRINT_DEBUG_MEM_HEX32(x)	print_debug_hex32(x)
+#define PRINT_DEBUG_MEM(x)		printk(BIOS_DEBUG, x)
+#define PRINT_DEBUG_MEM_HEX8(x)		printk(BIOS_DEBUG, "%02x", x)
+#define PRINT_DEBUG_MEM_HEX16(x)	printk(BIOS_DEBUG, "%04x", x)
+#define PRINT_DEBUG_MEM_HEX32(x)	printk(BIOS_DEBUG, "%08x", x)
 #define DUMPNORTH()			dump_pci_device(PCI_DEV(0, 0, 0))
 #else
 #define PRINT_DEBUG_MEM(x)
diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c
index 4434e57a78..4826fcf5b4 100644
--- a/src/northbridge/via/cn700/vga.c
+++ b/src/northbridge/via/cn700/vga.c
@@ -84,7 +84,7 @@ static void vga_init(device_t dev)
 
 #undef OLD_BOCHS_METHOD
 #ifdef OLD_BOCHS_METHOD
-	print_debug("Copying BOCHS BIOS to 0xf000\n");
+	printk(BIOS_DEBUG, "Copying BOCHS BIOS to 0xf000\n");
 	/*
 	 * Copy BOCHS BIOS from 4G-CONFIG_ROM_SIZE-64k (in flash) to 0xf0000 (in RAM)
 	 * This is for compatibility with the VGA ROM's BIOS callbacks.
diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c
index 7c77bff350..39e1753059 100644
--- a/src/northbridge/via/cx700/early_smbus.c
+++ b/src/northbridge/via/cx700/early_smbus.c
@@ -46,15 +46,6 @@
 
 #define SMBUS_DELAY()		outb(0x80, 0x80)
 
-/* Debugging macros. */
-#if CONFIG_DEBUG_SMBUS
-#define PRINT_DEBUG(x)		print_debug(x)
-#define PRINT_DEBUG_HEX16(x)	print_debug_hex16(x)
-#else
-#define PRINT_DEBUG(x)
-#define PRINT_DEBUG_HEX16(x)
-#endif
-
 /* Internal functions */
 #if CONFIG_DEBUG_SMBUS
 static void smbus_print_error(unsigned char host_status_register, int loops)
@@ -63,28 +54,26 @@ static void smbus_print_error(unsigned char host_status_register, int loops)
 	if (host_status_register == 0x00 || host_status_register == 0x40 ||
 	    host_status_register == 0x42)
 		return;
-	print_err("SMBus Error: ");
-	print_err_hex8(host_status_register);
+	printk(BIOS_ERR, "SMBus Error: %02x\n", host_status_register);
 
-	print_err("\n");
 	if (loops >= SMBUS_TIMEOUT) {
-		print_err("SMBus Timout\n");
+		printk(BIOS_ERR, "SMBus Timout\n");
 	}
 	if (host_status_register & (1 << 4)) {
-		print_err("Interrup/SMI# was Failed Bus Transaction\n");
+		printk(BIOS_ERR, "Interrup/SMI# was Failed Bus Transaction\n");
 	}
 	if (host_status_register & (1 << 3)) {
-		print_err("Bus Error\n");
+		printk(BIOS_ERR, "Bus Error\n");
 	}
 	if (host_status_register & (1 << 2)) {
-		print_err("Device Error\n");
+		printk(BIOS_ERR, "Device Error\n");
 	}
 	if (host_status_register & (1 << 1)) {
 		/* This isn't a real error... */
-		print_debug("Interrupt/SMI# was Successful Completion\n");
+		printk(BIOS_DEBUG, "Interrupt/SMI# was Successful Completion\n");
 	}
 	if (host_status_register & (1 << 0)) {
-		print_err("Host Busy\n");
+		printk(BIOS_ERR, "Host Busy\n");
 	}
 }
 #endif
@@ -239,9 +228,7 @@ static void dump_spd_data(const struct mem_controller *ctrl)
 	unsigned int val;
 
 	for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
-		print_debug("SPD Data for DIMM ");
-		print_debug_hex8(dimm);
-		print_debug("\n");
+		printk(BIOS_DEBUG, "SPD Data for DIMM %02x\n", dimm);
 
 		val = get_spd_data(ctrl, dimm, 0);
 		if (val == 0xff) {
@@ -249,15 +236,12 @@ static void dump_spd_data(const struct mem_controller *ctrl)
 		} else if (val == 0x80) {
 			regs = 128;
 		} else {
-			print_debug("No DIMM present\n");
+			printk(BIOS_DEBUG, "No DIMM present\n");
 			regs = 0;
 		}
 		for (offset = 0; offset < regs; offset++) {
-			print_debug("  Offset ");
-			print_debug_hex8(offset);
-			print_debug(" = 0x");
-			print_debug_hex8(get_spd_data(ctrl, dimm, offset));
-			print_debug("\n");
+			printk(BIOS_DEBUG, "  Offset %02x = 0x%02x\n",
+				offset, get_spd_data(ctrl, dimm, offset));
 		}
 	}
 }
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index a2e6dad01e..32be1ea4cd 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -972,7 +972,7 @@ static void step_20_21(const struct mem_controller *ctrl)
 		read32(0x102020);
 
 	/* Step 21. Normal operation */
-	print_spew("RAM Enable 5: Normal operation\n");
+	printk(BIOS_SPEW, "RAM Enable 5: Normal operation\n");
 	do_ram_command(ctrl, RAM_COMMAND_NORMAL);
 	udelay(3);
 }
@@ -988,58 +988,58 @@ static void step_2_19(const struct mem_controller *ctrl)
 	pci_write_config8(MEMCTRL, 0x69, val);
 
 	/* Step 3 Apply NOP. */
-	print_spew("RAM Enable 1: Apply NOP\n");
+	printk(BIOS_SPEW, "RAM Enable 1: Apply NOP\n");
 	do_ram_command(ctrl, RAM_COMMAND_NOP);
 
 	udelay(15);
 
 	// Step 4
-	print_spew("SEND: ");
+	printk(BIOS_SPEW, "SEND: ");
 	read32(0);
-	print_spew("OK\n");
+	printk(BIOS_SPEW, "OK\n");
 
 	// Step 5
 	udelay(400);
 
 	/* 6. Precharge all. Wait tRP. */
-	print_spew("RAM Enable 2: Precharge all\n");
+	printk(BIOS_SPEW, "RAM Enable 2: Precharge all\n");
 	do_ram_command(ctrl, RAM_COMMAND_PRECHARGE);
 
 	// Step 7
-	print_spew("SEND: ");
+	printk(BIOS_SPEW, "SEND: ");
 	read32(0);
-	print_spew("OK\n");
+	printk(BIOS_SPEW, "OK\n");
 
 	/* Step 8. Mode register set. */
-	print_spew("RAM Enable 4: Mode register set\n");
+	printk(BIOS_SPEW, "RAM Enable 4: Mode register set\n");
 	do_ram_command(ctrl, RAM_COMMAND_MRS);	//enable dll
 
 	// Step 9
-	print_spew("SEND: ");
+	printk(BIOS_SPEW, "SEND: ");
 
 	val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
 	if (val & DDR2_ODT_150ohm)
 		read32(0x102200);	//DDR2_ODT_150ohm
 	else
 		read32(0x102020);
-	print_spew("OK\n");
+	printk(BIOS_SPEW, "OK\n");
 
 	// Step 10
-	print_spew("SEND: ");
+	printk(BIOS_SPEW, "SEND: ");
 	read32(0x800);
-	print_spew("OK\n");
+	printk(BIOS_SPEW, "OK\n");
 
 	/* Step 11. Precharge all. Wait tRP. */
-	print_spew("RAM Enable 2: Precharge all\n");
+	printk(BIOS_SPEW, "RAM Enable 2: Precharge all\n");
 	do_ram_command(ctrl, RAM_COMMAND_PRECHARGE);
 
 	// Step 12
-	print_spew("SEND: ");
+	printk(BIOS_SPEW, "SEND: ");
 	read32(0x0);
-	print_spew("OK\n");
+	printk(BIOS_SPEW, "OK\n");
 
 	/* Step 13. Perform 8 refresh cycles. Wait tRC each time. */
-	print_spew("RAM Enable 3: CBR\n");
+	printk(BIOS_SPEW, "RAM Enable 3: CBR\n");
 	do_ram_command(ctrl, RAM_COMMAND_CBR);
 
 	/* JEDEC says only twice, do 8 times for posterity */
@@ -1047,14 +1047,14 @@ static void step_2_19(const struct mem_controller *ctrl)
 	for (i = 0; i < 8; i++) {
 		// Step 14
 		read32(0);
-		print_spew(".");
+		printk(BIOS_SPEW, ".");
 
 		// Step 15
 		udelay(100);
 	}
 
 	/* Step 17. Mode register set. Wait 200us. */
-	print_spew("\nRAM Enable 4: Mode register set\n");
+	printk(BIOS_SPEW, "\nRAM Enable 4: Mode register set\n");
 
 	//safe value for now, BL=8, WR=4, CAS=4
 	do_ram_command(ctrl, RAM_COMMAND_MRS);
diff --git a/src/northbridge/via/vx800/early_smbus.c b/src/northbridge/via/vx800/early_smbus.c
index f9b13eb88c..da2a55947e 100644
--- a/src/northbridge/via/vx800/early_smbus.c
+++ b/src/northbridge/via/vx800/early_smbus.c
@@ -50,42 +50,38 @@
 #define SMBUS_DELAY()		outb(0x80, 0x80)
 
 #if CONFIG_DEBUG_SMBUS
-#define PRINT_DEBUG(x)		print_debug(x)
-#define PRINT_DEBUG_HEX16(x)	print_debug_hex16(x)
+#define DEBUG(x...)		printk(BIOS_DEBUG, x)
 #else
-#define PRINT_DEBUG(x)
-#define PRINT_DEBUG_HEX16(x)
+#define DEBUG(x...)		while (0) { }
 #endif
 
 /* Internal functions */
 static void smbus_print_error(unsigned char host_status_register, int loops)
 {
-//              print_err("some i2c error\n");
+//              printk(BIOS_ERR, "some i2c error\n");
 	/* Check if there actually was an error */
 	if (host_status_register == 0x00 || host_status_register == 0x40 ||
 	    host_status_register == 0x42)
 		return;
-	print_err("smbus_error: ");
-	print_err_hex8(host_status_register);
-	print_err("\n");
+	printk(BIOS_ERR, "smbus_error: %02x\n", host_status_register);
 	if (loops >= SMBUS_TIMEOUT) {
-		print_err("SMBus Timout\n");
+		printk(BIOS_ERR, "SMBus Timout\n");
 	}
 	if (host_status_register & (1 << 4)) {
-		print_err("Interrup/SMI# was Failed Bus Transaction\n");
+		printk(BIOS_ERR, "Interrup/SMI# was Failed Bus Transaction\n");
 	}
 	if (host_status_register & (1 << 3)) {
-		print_err("Bus Error\n");
+		printk(BIOS_ERR, "Bus Error\n");
 	}
 	if (host_status_register & (1 << 2)) {
-		print_err("Device Error\n");
+		printk(BIOS_ERR, "Device Error\n");
 	}
 	if (host_status_register & (1 << 1)) {
 		/* This isn't a real error... */
-		print_debug("Interrupt/SMI# was Successful Completion\n");
+		printk(BIOS_DEBUG, "Interrupt/SMI# was Successful Completion\n");
 	}
 	if (host_status_register & (1 << 0)) {
-		print_err("Host Busy\n");
+		printk(BIOS_ERR, "Host Busy\n");
 	}
 }
 
@@ -185,11 +181,11 @@ void smbus_fixup(const struct mem_controller *mem_ctrl)
 
 	ram_slots = ARRAY_SIZE(mem_ctrl->channel0);
 	if (!ram_slots) {
-		print_err("smbus_fixup() thinks there are no RAM slots!\n");
+		printk(BIOS_ERR, "smbus_fixup() thinks there are no RAM slots!\n");
 		return;
 	}
 
-	PRINT_DEBUG("Waiting for SMBus to warm up");
+	DEBUG("Waiting for SMBus to warm up");
 
 	/*
 	 * Bad SPD data should be either 0 or 0xff, but YMMV. So we look for
@@ -207,13 +203,13 @@ void smbus_fixup(const struct mem_controller *mem_ctrl)
 		result = get_spd_data(mem_ctrl->channel0[current_slot],
 				      SPD_MEMORY_TYPE);
 		current_slot++;
-		PRINT_DEBUG(".");
+		DEBUG(".");
 	}
 
 	if (i >= SMBUS_TIMEOUT)
-		print_err("SMBus timed out while warming up\n");
+		printk(BIOS_ERR, "SMBus timed out while warming up\n");
 	else
-		PRINT_DEBUG("Done\n");
+		DEBUG("Done\n");
 }
 
 /* Debugging Function */
@@ -224,9 +220,7 @@ static void dump_spd_data(void)
 	unsigned int val;
 
 	for (dimm = 0; dimm < 8; dimm++) {
-		print_debug("SPD Data for DIMM ");
-		print_debug_hex8(dimm);
-		print_debug("\n");
+		printk(BIOS_DEBUG, "SPD Data for DIMM %02x\n", dimm);
 
 		val = get_spd_data(dimm, 0);
 		if (val == 0xff) {
@@ -234,16 +228,12 @@ static void dump_spd_data(void)
 		} else if (val == 0x80) {
 			regs = 128;
 		} else {
-			print_debug("No DIMM present\n");
+			printk(BIOS_DEBUG, "No DIMM present\n");
 			regs = 0;
 		}
-		for (offset = 0; offset < regs; offset++) {
-			print_debug("  Offset ");
-			print_debug_hex8(offset);
-			print_debug(" = 0x");
-			print_debug_hex8(get_spd_data(dimm, offset));
-			print_debug("\n");
-		}
+		for (offset = 0; offset < regs; offset++)
+			printk(BIOS_DEBUG, "  Offset %02x = 0x%02x\n",
+				offset, get_spd_data(dimm, offset));
 	}
 }
 #else
diff --git a/src/northbridge/via/vx800/raminit.c b/src/northbridge/via/vx800/raminit.c
index 6d58f785d3..a7a5757fd2 100644
--- a/src/northbridge/via/vx800/raminit.c
+++ b/src/northbridge/via/vx800/raminit.c
@@ -29,10 +29,10 @@
 #endif
 
 #if CONFIG_DEBUG_RAM_SETUP
-#define PRINT_DEBUG_MEM(x)		print_debug(x)
-#define PRINT_DEBUG_MEM_HEX8(x)		print_debug_hex8(x)
-#define PRINT_DEBUG_MEM_HEX16(x)	print_debug_hex16(x)
-#define PRINT_DEBUG_MEM_HEX32(x)	print_debug_hex32(x)
+#define PRINT_DEBUG_MEM(x)		printk(BIOS_DEBUG, x)
+#define PRINT_DEBUG_MEM_HEX8(x)		printk(BIOS_DEBUG, "%02x", x)
+#define PRINT_DEBUG_MEM_HEX16(x)	printk(BIOS_DEBUG, "%04x", x)
+#define PRINT_DEBUG_MEM_HEX32(x)	printk(BIOS_DEBUG, "%08x", x)
 #define DUMPNORTH()			dump_pci_device(PCI_DEV(0, 0, 0))
 #else
 #define PRINT_DEBUG_MEM(x)
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c
index b9fed6fc2b..78a1a88a19 100644
--- a/src/northbridge/via/vx900/chrome9hd.c
+++ b/src/northbridge/via/vx900/chrome9hd.c
@@ -296,9 +296,9 @@ static void chrome9hd_biosguide_init_seq(device_t dev)
 
 static void chrome9hd_init(device_t dev)
 {
-	print_debug("======================================================\n");
-	print_debug("== Chrome9 HD INIT\n");
-	print_debug("======================================================\n");
+	printk(BIOS_DEBUG, "======================================================\n");
+	printk(BIOS_DEBUG, "== Chrome9 HD INIT\n");
+	printk(BIOS_DEBUG, "======================================================\n");
 
 	chrome9hd_biosguide_init_seq(dev);
 
diff --git a/src/northbridge/via/vx900/early_smbus.c b/src/northbridge/via/vx900/early_smbus.c
index f006ce4ebb..e796d8d418 100644
--- a/src/northbridge/via/vx900/early_smbus.c
+++ b/src/northbridge/via/vx900/early_smbus.c
@@ -182,13 +182,13 @@ void dump_spd_data(spd_raw_data spd)
 	 * I originally saw this way to present SPD data in code from VIA. I
 	 * really liked the idea, so here it goes.
 	 */
-	print_debug("     00 01 02 03 04 05 06 07 07 09 0A 0B 0C 0D 0E 0F\n");
-	print_debug("---+------------------------------------------------");
+	printk(BIOS_DEBUG, "     00 01 02 03 04 05 06 07 07 09 0A 0B 0C 0D 0E 0F\n");
+	printk(BIOS_DEBUG, "---+------------------------------------------------");
 	for (i = 0; i < len; i++) {
 		reg = spd[i];
 		if ((i & 0x0f) == 0)
 			printk(BIOS_DEBUG, "\n%.2x |", i);
 		printk(BIOS_DEBUG, " %.2x", reg);
 	}
-	print_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 }
diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c
index 2896680b32..425fe77b15 100644
--- a/src/northbridge/via/vx900/early_vx900.c
+++ b/src/northbridge/via/vx900/early_vx900.c
@@ -69,7 +69,7 @@ void vx900_print_strapping_info(void)
 {
 	u8 strap = pci_read_config8(SNMIC, 0x56);
 
-	print_debug("VX900 strapping pins indicate that:\n");
+	printk(BIOS_DEBUG, "VX900 strapping pins indicate that:\n");
 	printk(BIOS_DEBUG, " ROM is on %s bus\n",
 	       (strap & (1 << 0)) ? "SPI" : "LPC");
 	printk(BIOS_DEBUG, " Auto reset is %s\n",
@@ -92,13 +92,13 @@ void vx900_print_strapping_info(void)
 void vx900_disable_auto_reboot(void)
 {
 	if (pci_read_config8(SNMIC, 0x56) & (1 << 1)) {
-		print_debug("Auto-reboot is disabled in hardware\n");
+		printk(BIOS_DEBUG, "Auto-reboot is disabled in hardware\n");
 		return;
 	}
 	/* Disable the GP3 timer, which is the root of all evil */
 	pci_write_config8(LPC, 0x98, 0);
 	/* Yep, that's all it takes */
-	print_debug("GP3 timer disabled."
+	printk(BIOS_DEBUG, "GP3 timer disabled."
 		    " Auto-reboot should not give you any more trouble.\n");
 }
 
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c
index ac5e4c840e..bb2f1b2745 100644
--- a/src/northbridge/via/vx900/lpc.c
+++ b/src/northbridge/via/vx900/lpc.c
@@ -146,7 +146,7 @@ static void vx900_lpc_ioapic_setup(device_t dev)
 		return;
 	}
 
-	print_debug("VX900 LPC: Setting up the south module IOAPIC.\n");
+	printk(BIOS_DEBUG, "VX900 LPC: Setting up the south module IOAPIC.\n");
 	/* Enable IOAPIC
 	 * So much work for one line of code. Talk about bloat :)
 	 * The 8259 PIC should still work even if the IOAPIC is enabled, so
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index f9c225d637..e1f744c280 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -80,7 +80,7 @@ static u64 vx900_get_top_of_ram(device_t mcu)
 static void killme_debug_4g_remap_reg(u32 reg32)
 {
 	if (reg32 & (1 << 0))
-		print_debug("Mem remapping enabled\n");
+		printk(BIOS_DEBUG, "Mem remapping enabled\n");
 	u64 remapstart = (reg32 >> 2) & 0x3ff;
 	u64 remapend = (reg32 >> 14) & 0x3ff;
 	remapstart <<= 26;
@@ -122,7 +122,7 @@ static u64 vx900_remap_above_4g(device_t mcu, u32 tolm)
 	 * becomes accessible at "to" to "until"
 	 */
 	if (tolm >= vx900_get_top_of_ram(mcu)) {
-		print_debug("Nothing to remap\n");
+		printk(BIOS_DEBUG, "Nothing to remap\n");
 	}
 
 	/* This is how the Vendor BIOS. Keep it for comparison for now */
@@ -220,11 +220,11 @@ static void vx900_set_resources(device_t dev)
 {
 	u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk;
 
-	print_debug("========================================"
+	printk(BIOS_DEBUG, "========================================"
 		    "========================================\n");
-	print_debug("============= VX900 memory sizing & Co. "
+	printk(BIOS_DEBUG, "============= VX900 memory sizing & Co. "
 		    "========================================\n");
-	print_debug("========================================"
+	printk(BIOS_DEBUG, "========================================"
 		    "========================================\n");
 
 	int idx = 10;
@@ -282,7 +282,7 @@ static void vx900_set_resources(device_t dev)
 
 	set_top_of_ram(tolmk << 10);
 
-	print_debug("======================================================\n");
+	printk(BIOS_DEBUG, "======================================================\n");
 	assign_resources(dev->link_list);
 }
 
diff --git a/src/northbridge/via/vx900/pcie.c b/src/northbridge/via/vx900/pcie.c
index 109e5c9ffe..b748c392d1 100644
--- a/src/northbridge/via/vx900/pcie.c
+++ b/src/northbridge/via/vx900/pcie.c
@@ -72,11 +72,11 @@ static void vx900_pcie_link_init(device_t dev)
 
 	pci_write_config8(dev, 0xa4, 0xff);
 	if (pci_read_config8(dev, 0x4a) & (1 << 3))
-		print_debug("Unsupported request detected.\n");
+		printk(BIOS_DEBUG, "Unsupported request detected.\n");
 
 	pci_write_config8(dev, 0x15a, 0xff);
 	if (pci_read_config8(dev, 0x15a) & (1 << 1))
-		print_debug("Negotiation pending.\n");
+		printk(BIOS_DEBUG, "Negotiation pending.\n");
 
 	/* Step 4: Read vendor ID */
 	/* FIXME: Do we want to run through the whole sequence and delay boot
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
index e6dace3b40..d1b2beb052 100644
--- a/src/northbridge/via/vx900/raminit_ddr3.c
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -1512,7 +1512,7 @@ static void vx900_dram_range(ramctr_timing * ctrl, rank_layout * ranks)
 		/* vvvvvvvvvv FIXME: Fix odd rank init vvvvvvvvvv */
 		if ((i & 1)) {
 			printk(BIOS_EMERG, "I cannot initialize rank %zu\n", i);
-			print_emerg("I have to disable it\n");
+			printk(BIOS_EMERG, "I have to disable it\n");
 			continue;
 		}
 		/* ^^^^^^^^^^ FIXME: Fix odd rank init ^^^^^^^^^^ */
diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c
index 63295e56c3..c5f36a8fdd 100644
--- a/src/northbridge/via/vx900/sata.c
+++ b/src/northbridge/via/vx900/sata.c
@@ -44,47 +44,47 @@ static void vx900_print_sata_errors(u32 flags)
 	       (flags & (1 << 27)) ? "detected" : "not detected");
 	/* Errors */
 	if (flags & (1 << 0))
-		print_debug("\tRecovered data integrity ERROR\n");
+		printk(BIOS_DEBUG, "\tRecovered data integrity ERROR\n");
 	if (flags & (1 << 1))
-		print_debug("\tRecovered data communication ERROR\n");
+		printk(BIOS_DEBUG, "\tRecovered data communication ERROR\n");
 	if (flags & (1 << 8))
-		print_debug("\tNon-recovered Transient Data Integrity ERROR\n");
+		printk(BIOS_DEBUG, "\tNon-recovered Transient Data Integrity ERROR\n");
 	if (flags & (1 << 9))
-		print_debug("\tNon-recovered Persistent Communication or"
+		printk(BIOS_DEBUG, "\tNon-recovered Persistent Communication or"
 			    "\tData Integrity ERROR\n");
 	if (flags & (1 << 10))
-		print_debug("\tProtocol ERROR\n");
+		printk(BIOS_DEBUG, "\tProtocol ERROR\n");
 	if (flags & (1 << 11))
-		print_debug("\tInternal ERROR\n");
+		printk(BIOS_DEBUG, "\tInternal ERROR\n");
 	if (flags & (1 << 17))
-		print_debug("\tPHY Internal ERROR\n");
+		printk(BIOS_DEBUG, "\tPHY Internal ERROR\n");
 	if (flags & (1 << 19))
-		print_debug("\t10B to 8B Decode ERROR\n");
+		printk(BIOS_DEBUG, "\t10B to 8B Decode ERROR\n");
 	if (flags & (1 << 20))
-		print_debug("\tDisparity ERROR\n");
+		printk(BIOS_DEBUG, "\tDisparity ERROR\n");
 	if (flags & (1 << 21))
-		print_debug("\tCRC ERROR\n");
+		printk(BIOS_DEBUG, "\tCRC ERROR\n");
 	if (flags & (1 << 22))
-		print_debug("\tHandshake ERROR\n");
+		printk(BIOS_DEBUG, "\tHandshake ERROR\n");
 	if (flags & (1 << 23))
-		print_debug("\tLink Sequence ERROR\n");
+		printk(BIOS_DEBUG, "\tLink Sequence ERROR\n");
 	if (flags & (1 << 24))
-		print_debug("\tTransport State Transition ERROR\n");
+		printk(BIOS_DEBUG, "\tTransport State Transition ERROR\n");
 	if (flags & (1 << 25))
-		print_debug("\tUNRECOGNIZED FIS type\n");
+		printk(BIOS_DEBUG, "\tUNRECOGNIZED FIS type\n");
 }
 
 static void vx900_dbg_sata_errors(device_t dev)
 {
 	/* Port 0 */
 	if (pci_read_config8(dev, 0xa0) & (1 << 0)) {
-		print_debug("Device detected in SATA port 0.\n");
+		printk(BIOS_DEBUG, "Device detected in SATA port 0.\n");
 		u32 flags = pci_read_config32(dev, 0xa8);
 		vx900_print_sata_errors(flags);
 	};
 	/* Port 1 */
 	if (pci_read_config8(dev, 0xa1) & (1 << 0)) {
-		print_debug("Device detected in SATA port 1.\n");
+		printk(BIOS_DEBUG, "Device detected in SATA port 1.\n");
 		u32 flags = pci_read_config32(dev, 0xac);
 		vx900_print_sata_errors(flags);
 	};
@@ -147,21 +147,18 @@ static void vx900_sata_write_phy_config(device_t dev, sata_phy_config cfg)
 
 static void vx900_sata_dump_phy_config(sata_phy_config cfg)
 {
-	print_debug("SATA PHY config:\n");
+	printk(BIOS_DEBUG, "SATA PHY config:\n");
 	int i;
 	for (i = 0; i < sizeof(sata_phy_config); i++) {
 		unsigned char val;
-		if ((i & 0x0f) == 0) {
-			print_debug_hex8(i);
-			print_debug_char(':');
-		}
+		if ((i & 0x0f) == 0)
+			printk(BIOS_DEBUG, "%02x:", i);
 		val = cfg[i];
 		if ((i & 7) == 0)
-			print_debug(" |");
-		print_debug_char(' ');
-		print_debug_hex8(val);
+			printk(BIOS_DEBUG, " |");
+		printk(BIOS_DEBUG, " %02x", val);
 		if ((i & 0x0f) == 0x0f) {
-			print_debug("\n");
+			printk(BIOS_DEBUG, "\n");
 		}
 	}
 }