Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

29 files changed, 285 insertions, 285 deletions

diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c
index 80dcc8d1a9..3fbc358de5 100644
--- a/src/northbridge/via/cn400/northbridge.c
+++ b/src/northbridge/via/cn400/northbridge.c
@@ -45,7 +45,7 @@ static void memctrl_init(device_t dev)
 	/* vlink mirror */
 	vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
 				    PCI_DEVICE_ID_VIA_CN400_VLINK, 0);
-	
+
 	/* Setup Low Memory Top */
 	/* 0x47 == HA(32:25)    */
 	/* 0x84/85 == HA(31:20) << 4 | DRAM Granularity */
@@ -104,7 +104,7 @@ static void memctrl_init(device_t dev)
 		pci_write_config8(vlink_dev, 0x63, shadowreg);
 
 	/* Activate VGA Frame Buffer */
-	
+
 	reg8 = pci_read_config8(dev, 0xA0);
 	reg8 |= 0x01;
 	pci_write_config8(dev, 0xA0, reg8);
@@ -268,7 +268,7 @@ static void cn400_domain_set_resources(device_t dev)
 			     (tolmk - 768 - CONFIG_VIDEO_MB * 1024));
 	}
 	assign_resources(&dev->link[0]);
-	
+
 	printk(BIOS_SPEW, "Leaving %s.\n", __func__);
 }
 
diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c
index a0b3aab1c5..7081c78744 100644
--- a/src/northbridge/via/cn400/raminit.c
+++ b/src/northbridge/via/cn400/raminit.c
@@ -19,7 +19,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-/* 
+/*
   Automatically detect and set up ddr dram on the CN400 chipset.
   Assumes DDR400 memory as no attempt is made to clock
   the chipset down if slower memory is installed.
@@ -33,9 +33,9 @@
 #include <cpu/x86/mtrr.h>
 #include "cn400.h"
 
-static void dimm_read(unsigned long bank,unsigned long x) 
+static void dimm_read(unsigned long bank,unsigned long x)
 {
-	//unsigned long eax; 
+	//unsigned long eax;
 	volatile unsigned long y;
 	//eax =  x;
 	y = * (volatile unsigned long *) (x+ bank) ;
@@ -50,7 +50,7 @@ static void print_val(char *str, int val)
 }
 
 /**
- * Configure the bus between the CPU and the northbridge. This might be able to 
+ * Configure the bus between the CPU and the northbridge. This might be able to
  * be moved to post-ram code in the future. For the most part, these registers
  * should not be messed around with. These are too complex to explain short of
  * copying the datasheets into the comments, but most of these values are from
@@ -66,27 +66,27 @@ static void c3_cpu_setup(device_t dev)
 	/* Host bus interface registers (D0F2 0x50-0x67) */
 	/* Taken from CN700 and updated from running CN400 */
 	uint8_t reg8;
-	
+
 	/* Host Bus I/O Circuit (see datasheet) */
 	/* Host Address Pullup/down Driving */
 	pci_write_config8(dev, 0x70, 0x33);
 	pci_write_config8(dev, 0x71, 0x44);
 	pci_write_config8(dev, 0x72, 0x33);
 	pci_write_config8(dev, 0x73, 0x44);
-	
+
 	/* Output Delay Stagger Control */
 	pci_write_config8(dev, 0x74, 0x70);
-	
+
 	/* AGTL+ I/O Circuit */
 	pci_write_config8(dev, 0x75, 0x08);
-	
+
 	/* AGTL+ Compensation Status */
 	pci_write_config8(dev, 0x76, 0x74);
-	
+
 	/* AGTL+ Auto Compensation Offest */
 	pci_write_config8(dev, 0x77, 0x00);
 	pci_write_config8(dev, 0x78, 0x94);
-	
+
 	/* Request phase control */
 	pci_write_config8(dev, 0x50, 0xA8);
 
@@ -94,71 +94,71 @@ static void c3_cpu_setup(device_t dev)
 	pci_write_config8(dev, 0x60, 0x00);
 	pci_write_config8(dev, 0x61, 0x00);
 	pci_write_config8(dev, 0x62, 0x00);
-	
+
 	/* QW DRDY# Timing Control */
 	pci_write_config8(dev, 0x63, 0x00);
 	pci_write_config8(dev, 0x64, 0x00);
 	pci_write_config8(dev, 0x65, 0x00);
-	
+
 	/* Read Line Burst DRDY# Timing Control */
 	pci_write_config8(dev, 0x66, 0x00);
 	pci_write_config8(dev, 0x67, 0x00);
-	
+
 	/* CPU Interface Control */
 	pci_write_config8(dev, 0x51, 0xFE);
 	pci_write_config8(dev, 0x52, 0xEF);
-	
+
 	/* Arbitration */
 	pci_write_config8(dev, 0x53, 0x88);
-		
+
 	/* Write Policy & Reorder Latecy */
 	pci_write_config8(dev, 0x56, 0x00);
-	
+
 	/* Delivery-Trigger Control */
 	pci_write_config8(dev, 0x58, 0x00);
-		
+
 	/* IPI Control */
 	pci_write_config8(dev, 0x59, 0x30);
-	
+
 	/* CPU Misc Control */
 	pci_write_config8(dev, 0x5C, 0x00);
-	
+
 	/* Write Policy */
 	pci_write_config8(dev, 0x5d, 0xb2);
-	
+
 	/* Bandwidth Timer */
 	pci_write_config8(dev, 0x5e, 0x88);
-	
+
 	/* CPU Miscellaneous Control */
 	pci_write_config8(dev, 0x5f, 0xc7);
-	
+
 	/* CPU Miscellaneous Control */
 	pci_write_config8(dev, 0x55, 0x28);
 	pci_write_config8(dev, 0x57, 0x69);
-	
+
 	/* CPU Host Bus Final Setup */
 	reg8 = pci_read_config8(dev, 0x54);
 	reg8 |= 0x08;
 	pci_write_config8(dev, 0x54, reg8);
 
 }
- 
-static void ddr_ram_setup(void) 
+
+static void ddr_ram_setup(void)
 {
 	uint8_t b, c, bank, ma;
 	uint16_t i;
 	unsigned long bank_address;
-	
-	
-	print_debug("CN400 RAM init starting\n");	
+
+
+	print_debug("CN400 RAM init starting\n");
 
 	pci_write_config8(ctrl.d0f7, 0x75, 0x08);
-	
-		
+
+
 	/* No  Interleaving or Multi Page */
 	pci_write_config8(ctrl.d0f3, 0x69, 0x00);
-	pci_write_config8(ctrl.d0f3, 0x6b, 0x10);	
-	
+	pci_write_config8(ctrl.d0f3, 0x6b, 0x10);
+
 /*
     DRAM MA Map Type  Device 0  Fn3 Offset 50-51
 
@@ -186,14 +186,14 @@ static void ddr_ram_setup(void)
 		bank = 0x40;
 		b = smbus_read_byte(0x50, SPD_NUM_ROWS);
 		//print_val("\nNumber of Rows ", b);
-		
+
 		if( b >= 0x0d ){	// 256/512Mb
-		
+
 			if (b == 0x0e)
 				bank = 0x48;
 			else
 				bank = 0x44;
-			 
+
 			/*
     			Read SPD byte 13, Primary DRAM width.
 			*/
@@ -205,7 +205,7 @@ static void ddr_ram_setup(void)
 
 		/*
     		Read SPD byte 4, Number of column addresses.
-		*/		
+		*/
 		b = smbus_read_byte(0x50, SPD_NUM_COLUMNS);
 		//print_val("\nNo Columns ",b);
 		if( b == 10 || b == 11 || b == 12) c |= 0x60;   // 10/11 bit col addr
@@ -240,11 +240,11 @@ static void ddr_ram_setup(void)
 	//c = 0;
 	b = smbus_read_byte(0x50, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
 	if( b & 0x02 )
-	{ 
+	{
 		c = 0x40;         				// 2GB
 		bank |= 0x02;
 	}
-	else if( b & 0x01) 
+	else if( b & 0x01)
 	{
 		c = 0x20;    					// 1GB
 		if (bank == 0x48) bank |= 0x01;
@@ -255,12 +255,12 @@ static void ddr_ram_setup(void)
 		c = 0x10;    					// 512MB
 		if (bank == 0x44) bank |= 0x02;
 	}
-	else if( b & 0x40) 
-	{	
+	else if( b & 0x40)
+	{
 		c = 0x08;    					// 256MB
 		if (bank == 0x44) bank |= 0x01;
 		else bank |= 0x03;
-	} 
+	}
 	else if( b & 0x20)
 	{
 		c = 0x04;    					// 128MB
@@ -276,7 +276,7 @@ static void ddr_ram_setup(void)
 
 	// set bank zero size
 	pci_write_config8(ctrl.d0f3, 0x40, c);
-	
+
 	// SPD byte 5  # of physical banks
 	b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS);
 
@@ -288,7 +288,7 @@ static void ddr_ram_setup(void)
 	}
 /*	else
 	{
-		die("Only a single DIMM is supported by EPIA-N(L)\n");	
+		die("Only a single DIMM is supported by EPIA-N(L)\n");
 	}
 */
 	// set banks 1,2,3...
@@ -299,13 +299,13 @@ static void ddr_ram_setup(void)
 	pci_write_config8(ctrl.d0f3, 0x45,c);
 	pci_write_config8(ctrl.d0f3, 0x46,c);
 	pci_write_config8(ctrl.d0f3, 0x47,c);
-	
+
 	/* Top Rank Address Mirrored to the South Bridge */
 	/* over the VLink								 */
 	pci_write_config8(ctrl.d0f7, 0x57, (c << 1));
 
 	ma = bank;
-		
+
 	/* Read SPD byte 18 CAS Latency */
 	b = smbus_read_byte(0x50, SPD_ACCEPTABLE_CAS_LATENCIES);
 /*	print_debug("\nCAS Supported ");
@@ -322,7 +322,7 @@ static void ddr_ram_setup(void)
 	print_val("\nCycle time at CL X-0.5 (nS)", c);
 	c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD);
 	print_val("\nCycle time at CL X-1   (nS)", c);
-*/	
+*/
 	/* Scaling of Cycle Time SPD data */
 	/* 7      4 3       0             */
 	/*    ns     x0.1ns               */
@@ -353,7 +353,7 @@ static void ddr_ram_setup(void)
 				c = 0x10;
 			}
 		}
-	}	
+	}
 
 	/* Scale DRAM Cycle Time to tRP/tRCD */
 	/* 7      2 1       0             */
@@ -384,7 +384,7 @@ static void ddr_ram_setup(void)
 */
 
 	b = smbus_read_byte(0x50, SPD_MIN_ROW_PRECHARGE_TIME);
-	
+
 	//print_val("\ntRP ",b);
 	if ( b >= (5 * bank)) {
 		c |= 0x03;		// set tRP = 5T
@@ -425,16 +425,16 @@ static void ddr_ram_setup(void)
 	if ( b >= (9 * bank)) c |= 0xC0;		// set tRAS = 9T
 	else if ( b >= (8 * bank)) c |= 0x80;	// set tRAS = 8T
 	else if ( b >= (7 * bank)) c |= 0x40;	// set tRAS = 7T
-	
+
 	/* Write DRAM Timing All Banks I */
 	pci_write_config8(ctrl.d0f3, 0x56, c);
-	
+
 	/* TWrite DRAM Timing All Banks II */
 	pci_write_config8(ctrl.d0f3, 0x57, 0x1a);
-	
+
 	/* DRAM arbitration timer */
 	pci_write_config8(ctrl.d0f3, 0x65, 0x99);
-		
+
 /*
     DRAM Clock  Device 0 Fn 3 Offset 68
 */
@@ -453,7 +453,7 @@ static void ddr_ram_setup(void)
 		/* 133MHz FSB / DDR333.  See also c3_cpu_setup */
 		pci_write_config8(ctrl.d0f3, 0x68, 0x81);
 	}
-	else 
+	else
 	{
 		/* DRAM DDR Control Alert! Alert! This hardwires to */
 		/* 133MHz FSB / DDR266.  See also c3_cpu_setup */
@@ -475,7 +475,7 @@ static void ddr_ram_setup(void)
 
 	/* 4-Way Interleave With Multi-Paging (From Running System)*/
 	pci_write_config8(ctrl.d0f3, 0x69, c);
-	
+
 	/*DRAM Controller Internal Options */
 	pci_write_config8(ctrl.d0f3, 0x54, 0x01);
 
@@ -484,7 +484,7 @@ static void ddr_ram_setup(void)
 
 	/* DRAM Control */
 	pci_write_config8(ctrl.d0f3, 0x6e, 0x80);
-	
+
 	/* Disable refresh for now */
 	pci_write_config8(ctrl.d0f3, 0x6a, 0x00);
 
@@ -497,7 +497,7 @@ static void ddr_ram_setup(void)
 
 	/* DRAM Bus Turn-Around Setting */
 	pci_write_config8(ctrl.d0f3, 0x60, 0x01);
-	
+
 	/* Disable DRAM refresh */
 	pci_write_config8(ctrl.d0f3,0x6a,0x0);
 
@@ -524,7 +524,7 @@ static void ddr_ram_setup(void)
 	c = b | 0x40;
 
 	pci_write_config8(ctrl.d0f3, 0xb0, c);
-	
+
 	/* Set RAM Decode method */
 	pci_write_config8(ctrl.d0f3, 0x55, 0x0a);
 
@@ -542,14 +542,14 @@ static void ddr_ram_setup(void)
 
 			CPU FSB Operating Frequency (bits 7:5)
 	    	  	000 : 100MHz    001 : 133MHz
-	    	  	010 : 200MHz    
+	    	  	010 : 200MHz
 			  	011->111 : Reserved
-		  
+
 			SDRAM BL8 (4)
-			
+
 			Don't change Frequency from power up defaults
 			This seems to lockup the RAM interface
-		*/	
+		*/
 		c = pci_read_config8(ctrl.d0f2, 0x54);
 		c |= 0x10;
 		pci_write_config8(ctrl.d0f2, 0x54, c);
@@ -566,7 +566,7 @@ static void ddr_ram_setup(void)
 		c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 		c &= 0xf8;		/* Clear bits 2-0. */
 		c |= RAM_COMMAND_NOP;
-		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);		
+		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 
 		/* read a double word from any address of the dimm */
 		dimm_read(bank_address,0x1f000);
@@ -576,7 +576,7 @@ static void ddr_ram_setup(void)
 		c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 		c &= 0xf8;		/* Clear bits 2-0. */
 		c |= RAM_COMMAND_PRECHARGE;
-		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);		
+		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 		dimm_read(bank_address,0x1f000);
 
 
@@ -584,8 +584,8 @@ static void ddr_ram_setup(void)
 		c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 		c &= 0xf8;		/* Clear bits 2-0. */
 		c |= RAM_COMMAND_MSR_LOW;
-		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);	
-		/* TODO: Bank Addressing for Different Numbers of Row Addresses */	
+		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
+		/* TODO: Bank Addressing for Different Numbers of Row Addresses */
 		dimm_read(bank_address,0x2000);
 		udelay(1);
 		dimm_read(bank_address,0x800);
@@ -595,14 +595,14 @@ static void ddr_ram_setup(void)
 		c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 		c &= 0xf8;		/* Clear bits 2-0. */
 		c |= RAM_COMMAND_PRECHARGE;
-		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);		
+		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 		dimm_read(bank_address,0x1f200);
 
 		/* CBR Cycle Enable */
 		c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 		c &= 0xf8;		/* Clear bits 2-0. */
 		c |= RAM_COMMAND_CBR;
-		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);		
+		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 
 		/* Read 8 times */
 		for (c=0;c<8;c++) {
@@ -614,10 +614,10 @@ static void ddr_ram_setup(void)
 		c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 		c &= 0xf8;		/* Clear bits 2-0. */
 		c |= RAM_COMMAND_MSR_LOW;
-		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);		
+		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 
 
-/* 
+/*
     Mode Register Definition
     with adjustement so that address calculation is correct - 64 bit technology, therefore
     a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented
@@ -626,9 +626,9 @@ static void ddr_ram_setup(void)
     MR[9-7]   CAS Latency
     MR[6]     Burst Type 0 = sequential, 1 = interleaved
     MR[5-3]   burst length 001 = 2, 010 = 4, 011 = 8, others reserved
-    MR[0-2]   dont care 
+    MR[0-2]   dont care
 
-    CAS Latency 
+    CAS Latency
     000       reserved
     001       reserved
     010       2
@@ -657,24 +657,24 @@ static void ddr_ram_setup(void)
 		c &= 0xf8;		/* Clear bits 2-0. */
 		c |= RAM_COMMAND_NORMAL;
 		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
-				
+
 		bank_address = pci_read_config8(ctrl.d0f3,0x40+bank) * 0x2000000;
 	} // end of for each bank
 
-	
+
 	/* Set DRAM DQS Output Control */
 	pci_write_config8(ctrl.d0f3, 0x79, 0x11);
-	
+
 	/* Set DQS A/B Input delay to defaults */
 	pci_write_config8(ctrl.d0f3, 0x7A, 0xA1);
-	pci_write_config8(ctrl.d0f3, 0x7B, 0x62);	
+	pci_write_config8(ctrl.d0f3, 0x7B, 0x62);
 
 	/* DQS Duty Cycle Control */
 	pci_write_config8(ctrl.d0f3, 0xED, 0x11);
 
 	/* SPD byte 5  # of physical banks */
 	b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1;
-	
+
 	/* determine low bond */
 	if( b == 2)
 		bank_address = pci_read_config8(ctrl.d0f3,0x40) * 0x2000000;
@@ -720,10 +720,10 @@ static void ddr_ram_setup(void)
 
 		// if everything verified then found low bond
 		break;
-		
+
 	}
-	print_val("\nLow Bond ",i);	
-	if( i < 0xff ){ 
+	print_val("\nLow Bond ",i);
+	if( i < 0xff ){
 		c = i++;
 		for(  ; i <0xff ; i++){
 			pci_write_config8(ctrl.d0f3,0x70, i);
@@ -774,24 +774,24 @@ static void ddr_ram_setup(void)
 
 	/* Set DQS ChA Data Output Delay to the default */
 	pci_write_config8(ctrl.d0f3, 0x71, 0x65);
-	
+
 	/* Set Ch B DQS Output Delays */
 	pci_write_config8(ctrl.d0f3, 0x72, 0x2a);
 	pci_write_config8(ctrl.d0f3, 0x73, 0x29);
-	
+
 	pci_write_config8(ctrl.d0f3, 0x78, 0x03);
 
 	/* Mystery Value */
 	pci_write_config8(ctrl.d0f3, 0x67, 0x50);
-	
+
 	/* Enable Toggle Limiting */
 	pci_write_config8(ctrl.d0f4, 0xA3, 0x80);
-	
+
 /*
     DRAM refresh rate  Device 0 F3 Offset 6a
-	TODO :: Fix for different DRAM technologies 
-	other than 512Mb and DRAM Freq 
-    Units of 16 DRAM clock cycles - 1. 
+	TODO :: Fix for different DRAM technologies
+	other than 512Mb and DRAM Freq
+    Units of 16 DRAM clock cycles - 1.
 */
 	//c = pci_read_config8(ctrl.d0f3, 0x68);
 	//c &= 0x07;
@@ -799,13 +799,13 @@ static void ddr_ram_setup(void)
 	//print_val("SPD_REFRESH = ", b);
 
 	pci_write_config8(ctrl.d0f3,0x6a,0x65);
-	
+
 	/* SMM and APIC decoding, we do not use SMM */
 	b = 0x29;
 	pci_write_config8(ctrl.d0f3, 0x86, b);
 	/* SMM and APIC decoding mirror */
 	pci_write_config8(ctrl.d0f7, 0xe6, b);
-	
+
 	/* Open Up the Rest of the Shadow RAM */
 	pci_write_config8(ctrl.d0f3,0x80,0xff);
 	pci_write_config8(ctrl.d0f3,0x81,0xff);
@@ -816,10 +816,10 @@ static void ddr_ram_setup(void)
 	pci_write_config8(ctrl.d0f7,0x76,0x50);
 
 	pci_write_config8(ctrl.d0f7,0x71,0xc8);
-	
+
 
 	/* VGA device. */
 	pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15));
 	pci_write_config16(ctrl.d0f3, 0xa4, 0x0010);
     print_debug("CN400 raminit.c done\n");
-}	
+}
diff --git a/src/northbridge/via/cn400/vga.c b/src/northbridge/via/cn400/vga.c
index cf9c54be23..511079b03a 100644
--- a/src/northbridge/via/cn400/vga.c
+++ b/src/northbridge/via/cn400/vga.c
@@ -62,7 +62,7 @@ static int via_cn400_int15_handler(struct eregs *regs)
 	case 0x5f02:
 		regs->eax=0x5f;
 		regs->ebx= (regs->ebx & 0xffff0000) | 2;
-		regs->ecx= (regs->ecx & 0xffff0000) | 0x401;  // PAL + crt only 
+		regs->ecx= (regs->ecx & 0xffff0000) | 0x401;  // PAL + crt only
 		regs->edx= (regs->edx & 0xffff0000) | 0;  // TV Layout - default
 		res=0;
 		break;
@@ -70,7 +70,7 @@ static int via_cn400_int15_handler(struct eregs *regs)
 		regs->eax=0x860f;
 		break;
         default:
-		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", 
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
 				regs->eax & 0xffff);
 		break;
 	}
diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index 63dab5b3e0..20b0afeb6e 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -51,7 +51,7 @@ static void do_ram_command(device_t dev, u8 command)
 }
 
 /**
- * Configure the bus between the CPU and the northbridge. This might be able to 
+ * Configure the bus between the CPU and the northbridge. This might be able to
  * be moved to post-ram code in the future. For the most part, these registers
  * should not be messed around with. These are too complex to explain short of
  * copying the datasheets into the comments, but most of these values are from
@@ -244,7 +244,7 @@ static void sdram_set_size(const struct mem_controller *ctrl)
 }
 
 /**
- * Set up various RAM and other control registers statically. Some of these may 
+ * Set up various RAM and other control registers statically. Some of these may
  * not be needed, other should be done with SPD info, but that's a project for
  * the future.
  */
@@ -422,7 +422,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
 	PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
 	/* Safe value for now, BL=8, WR=5, CAS=4 */
 	/*
-	 * (E)MRS values are from the BPG. No direct explanation is given, but 
+	 * (E)MRS values are from the BPG. No direct explanation is given, but
 	 * they should somehow conform to the JEDEC DDR2 SDRAM Specification
 	 * (JESD79-2C).
 	 */
diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c
index 69f188b01e..33d1fe0071 100644
--- a/src/northbridge/via/cn700/vga.c
+++ b/src/northbridge/via/cn700/vga.c
@@ -62,7 +62,7 @@ static int via_cn700_int15_handler(struct eregs *regs)
 	case 0x5f02:
 		regs->eax=0x5f;
 		regs->ebx= (regs->ebx & 0xffff0000) | 2;
-		regs->ecx= (regs->ecx & 0xffff0000) | 0x401;  // PAL + crt only 
+		regs->ecx= (regs->ecx & 0xffff0000) | 0x401;  // PAL + crt only
 		regs->edx= (regs->edx & 0xffff0000) | 0;  // TV Layout - default
 		res=0;
 		break;
@@ -70,7 +70,7 @@ static int via_cn700_int15_handler(struct eregs *regs)
 		regs->eax=0x860f;
 		break;
         default:
-		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", 
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
 				regs->eax & 0xffff);
 		break;
 	}
diff --git a/src/northbridge/via/cx700/cx700_early_serial.c b/src/northbridge/via/cx700/cx700_early_serial.c
index a0d7301e20..3f5020f670 100644
--- a/src/northbridge/via/cx700/cx700_early_serial.c
+++ b/src/northbridge/via/cx700/cx700_early_serial.c
@@ -61,7 +61,7 @@ static void enable_cx700_serial(void)
 	// turn on pnp
 	cx700_writepnpaddr(0x87);
 	cx700_writepnpaddr(0x87);
-	// now go ahead and set up com1. 
+	// now go ahead and set up com1.
 	// set address
 	cx700_writepnpaddr(0x7);
 	cx700_writepnpdata(0x2);
diff --git a/src/northbridge/via/cx700/cx700_vga.c b/src/northbridge/via/cx700/cx700_vga.c
index e36062d9d2..2999907616 100644
--- a/src/northbridge/via/cx700/cx700_vga.c
+++ b/src/northbridge/via/cx700/cx700_vga.c
@@ -120,7 +120,7 @@ static int via_cx700_int15_handler(struct eregs *regs)
 		break;
 
         default:
-		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", 
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
 				regs->eax & 0xffff);
 		break;
 	}
@@ -170,7 +170,7 @@ static void vga_init(device_t dev)
 	//   call_bios_interrupt(0x10,0x4f1f,0x8003,1,0);
 	// this is how it looks:
 	vga_enable_console();
-	
+
 	/* It's not clear if these need to be programmed before or after
 	 * the VGA bios runs. Try both, clean up later */
 	/* Set memory rate to 200MHz */
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index 6693724ad4..5694ea31aa 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -452,7 +452,7 @@ static void sdram_set_safe_values(const struct mem_controller *ctrl)
 	/* To store DDRII frequence */
 	pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ, val);
 
-	/* Manual reset and adjust DLL when DRAM change frequency 
+	/* Manual reset and adjust DLL when DRAM change frequency
 	 * This is a necessary sequence.
 	 */
 	udelay(2000);
@@ -1623,7 +1623,7 @@ static void sdram_enable(const struct mem_controller *ctrl)
 		u8 mask;
 		u8 val;
 	} b0d1f0[] = {
-		{ 0x40, 0x00, 0x8b}, 
+		{ 0x40, 0x00, 0x8b},
 		{ 0x41, 0x80, 0x43},
 		{ 0x42, 0x00, 0x62},
 		{ 0x43, 0x00, 0x44},
diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c
index 5af7836a93..8fca0eae2c 100644
--- a/src/northbridge/via/vt8601/northbridge.c
+++ b/src/northbridge/via/vt8601/northbridge.c
@@ -18,7 +18,7 @@
  * slower than normal, ethernet drops packets).
  * Apparently these registers govern some sort of bus master behavior.
  */
-static void northbridge_init(device_t dev) 
+static void northbridge_init(device_t dev)
 {
 	printk(BIOS_SPEW, "VT8601 random fixup ...\n");
 	pci_write_config8(dev, 0x70, 0xc0);
@@ -108,16 +108,16 @@ static void pci_domain_set_resources(device_t dev)
 		for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 			unsigned char reg;
 			reg = pci_read_config8(mc_dev, ramregs[i]);
-			/* these are ENDING addresses, not sizes. 
+			/* these are ENDING addresses, not sizes.
 			 * if there is memory in this slot, then reg will be > rambits.
-			 * So we just take the max, that gives us total. 
+			 * So we just take the max, that gives us total.
 			 * We take the highest one to cover for once and future coreboot
 			 * bugs. We warn about bugs.
 			 */
 			if (reg > rambits)
 				rambits = reg;
 			if (reg < rambits)
-				printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", 
+				printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
 					ramregs[i]);
 		}
 		printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
@@ -149,7 +149,7 @@ static struct device_operations pci_domain_ops = {
         .enable_resources = enable_childrens_resources,
         .init             = 0,
         .scan_bus         = pci_domain_scan_bus,
-};  
+};
 
 static void cpu_bus_init(device_t dev)
 {
@@ -182,5 +182,5 @@ static void enable_dev(struct device *dev)
 
 struct chip_operations northbridge_via_vt8601_ops = {
 	CHIP_NAME("VIA VT8601 Northbridge")
-	.enable_dev = enable_dev, 
+	.enable_dev = enable_dev,
 };
diff --git a/src/northbridge/via/vt8601/raminit.c b/src/northbridge/via/vt8601/raminit.c
index cb13ad4e98..2365b8d8fb 100644
--- a/src/northbridge/via/vt8601/raminit.c
+++ b/src/northbridge/via/vt8601/raminit.c
@@ -13,7 +13,7 @@ U.S. Government has rights to use, reproduce, and distribute this
 SOFTWARE.  The public may copy, distribute, prepare derivative works
 and publicly display this SOFTWARE without charge, provided that this
 Notice and any statement of authorship are reproduced on all copies.
-Neither the Government nor the University makes any warranty, express 
+Neither the Government nor the University makes any warranty, express
 or implied, or assumes any liability or responsibility for the use of
 this SOFTWARE.  If SOFTWARE is modified to produce derivative works,
 such modified SOFTWARE should be clearly marked, so as not to confuse
@@ -107,14 +107,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 	pci_write_config8(north, 0x78, 0x01);
 	print_debug_hex8(pci_read_config8(north, 0x78));
 
-	// dram control, see the book. 
+	// dram control, see the book.
 #if DIMM_PC133
 	pci_write_config8(north, 0x68, 0x52);
 #else
 	pci_write_config8(north, 0x68, 0x42);
 #endif
 
-	// dram control, see the book. 
+	// dram control, see the book.
 	pci_write_config8(north, 0x6B, 0x0c);
 
 	// Initial setting, 256MB in each bank, will be rewritten later.
@@ -125,7 +125,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 	pci_write_config8(north, 0x5D, 0x80);
 	pci_write_config8(north, 0x5E, 0xA0);
 	pci_write_config8(north, 0x5F, 0xC0);
-	// It seems we have to take care of these 2 registers as if 
+	// It seems we have to take care of these 2 registers as if
 	// they are bank 6 and 7.
 	pci_write_config8(north, 0x56, 0xC0);
 	pci_write_config8(north, 0x57, 0xC0);
@@ -149,7 +149,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 #endif
 
 	// dram frequency select.
-	// enable 4K pages for 64M dram. 
+	// enable 4K pages for 64M dram.
 #if DIMM_PC133
 	pci_write_config8(north, 0x69, 0x3c);
 #else
@@ -181,8 +181,8 @@ static unsigned long spd_module_size(unsigned char slot)
 	/* unsigned int module = ((0x50 + slot) << 1) + 1; */
 	unsigned int module = 0x50 + slot;
 
-	/* is the module there? if byte 2 is not 4, then we'll assume it 
-	 * is useless. 
+	/* is the module there? if byte 2 is not 4, then we'll assume it
+	 * is useless.
 	 */
 	print_info("Slot ");
 	print_info_hex8(slot);
@@ -292,7 +292,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	pci_write_config8(north, 0x6C, 0x01);
 	print_debug("NOP\n");
 	/* wait 200us */
-	// You need to do the memory reference. That causes the nop cycle. 
+	// You need to do the memory reference. That causes the nop cycle.
 	dimms_read(0);
 	udelay(400);
 	print_debug("PRECHARGE\n");
@@ -340,7 +340,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	dimms_read(0);
 	udelay(200);
 	print_debug("set ref. rate\n");
-	// Set the refresh rate. 
+	// Set the refresh rate.
 #if DIMM_PC133
 	pci_write_config8(north, 0x6A, 0x86);
 #else
@@ -370,7 +370,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 		/* Set the MA map type.
 		 *
-		 * 0xa should be another option, but when 
+		 * 0xa should be another option, but when
 		 * it would be used is unknown.
 		 */
 
diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c
index 4920ec3973..7ba9cd6316 100644
--- a/src/northbridge/via/vt8623/northbridge.c
+++ b/src/northbridge/via/vt8623/northbridge.c
@@ -21,7 +21,7 @@
  * Apparently these registers govern some sort of bus master behavior.
  */
 
-static void northbridge_init(device_t dev) 
+static void northbridge_init(device_t dev)
 {
 	device_t fb_dev;
 	unsigned long fb;
@@ -40,7 +40,7 @@ static void northbridge_init(device_t dev)
 	pci_write_config8(dev,  0x84, 0x80);
 	pci_write_config16(dev, 0x80, 0x610f);
 	pci_write_config32(dev, 0x88, 0x00000002);
-	
+
 	fb_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0);
 	if (fb_dev) {
 		/* Fixup GART and framebuffer addresses properly.
@@ -168,16 +168,16 @@ static void pci_domain_set_resources(device_t dev)
 		for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 			unsigned char reg;
 			reg = pci_read_config8(mc_dev, ramregs[i]);
-			/* these are ENDING addresses, not sizes. 
+			/* these are ENDING addresses, not sizes.
 			 * if there is memory in this slot, then reg will be > rambits.
-			 * So we just take the max, that gives us total. 
+			 * So we just take the max, that gives us total.
 			 * We take the highest one to cover for once and future coreboot
 			 * bugs. We warn about bugs.
 			 */
 			if (reg > rambits)
 				rambits = reg;
 			if (reg < rambits)
-				printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", 
+				printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
 					ramregs[i]);
 		}
 		printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
@@ -210,7 +210,7 @@ static struct device_operations pci_domain_ops = {
         .enable_resources = enable_childrens_resources,
         .init             = 0,
         .scan_bus         = pci_domain_scan_bus,
-};  
+};
 
 static void cpu_bus_init(device_t dev)
 {
diff --git a/src/northbridge/via/vt8623/raminit.c b/src/northbridge/via/vt8623/raminit.c
index f57127b3da..295011b785 100644
--- a/src/northbridge/via/vt8623/raminit.c
+++ b/src/northbridge/via/vt8623/raminit.c
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-/* 
+/*
   Automatically detect and set up ddr dram on the CLE266 chipset.
   Assumes DDR memory, though chipset also supports SDRAM
   Assumes at least 266Mhz memory as no attempt is made to clock
@@ -35,9 +35,9 @@
 
 
 
-void dimm_read(unsigned long bank,unsigned long x) 
+void dimm_read(unsigned long bank,unsigned long x)
 {
-	//unsigned long eax; 
+	//unsigned long eax;
 	volatile unsigned long y;
 	//eax =  x;
 	y = * (volatile unsigned long *) (x+ bank) ;
@@ -46,7 +46,7 @@ void dimm_read(unsigned long bank,unsigned long x)
 
 
 void
-dumpnorth(device_t north) 
+dumpnorth(device_t north)
 {
 	uint16_t r, c;
 	for(r = 0; r < 256; r += 16) {
@@ -65,7 +65,7 @@ void print_val(char *str, int val)
 	print_debug_hex8(val);
 }
 
-static void ddr_ram_setup(const struct mem_controller *ctrl) 
+static void ddr_ram_setup(const struct mem_controller *ctrl)
 {
 	device_t north = (device_t) 0;
 	uint8_t b, c, bank;
@@ -75,7 +75,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 	print_debug("vt8623 init starting\n");
 	north = pci_locate_device(PCI_ID(0x1106, 0x3123), 0);
 	north = 0;
-	
+
 
 	pci_write_config8(north,0x75,0x08);
 
@@ -105,7 +105,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 	print_val("Detecting Memory\nNumber of Banks ",b);
 
 	if( b != 2 ){            // not 16 Mb type
-	
+
 /*
     Read SPD byte 3, Number of row addresses.
 */
@@ -126,7 +126,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
     64/128Mb chip
 
     Read SPD byte 4, Number of column addresses.
-*/		
+*/
 		b = smbus_read_byte(0xa0,4);
 		print_val("\nNo Columns ",b);
 		if( b == 10 || b == 11 ) c |= 0x60;   // 10/11 bit col addr
@@ -153,7 +153,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 	if( b & 0x02 ) c = 0x80;         // 2GB
 	else if( b & 0x01) c = 0x40;     // 1GB
 	else if( b & 0x80) c = 0x20;     // 512Mb
-	else if( b & 0x40) c = 0x10;     // 256Mb 
+	else if( b & 0x40) c = 0x10;     // 256Mb
 	else if( b & 0x20) c = 0x08;     // 128Mb
 	else if( b & 0x10) c = 0x04;     // 64Mb
 	else if( b & 0x08) c = 0x02;     // 32Mb
@@ -191,7 +191,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 	print_val("\nCycle time at CL X     (nS)",smbus_read_byte(0xa0,9));
 	print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23));
 	print_val("\nCycle time at CL X-1   (nS)",smbus_read_byte(0xa0,25));
-	
+
 
 	if( b & 0x10 ){             // DDR offering optional CAS 3
 		print_debug("\nStarting at CAS 3");
@@ -405,7 +405,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 		/* MSR Enable */
 		pci_write_config8(north,0x6b,0x13);
 
-/* 
+/*
     Mode Register Definition
     with adjustement so that address calculation is correct - 64 bit technology, therefore
     a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented
@@ -414,9 +414,9 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
     MR[9-7]   CAS Latency
     MR[6]     Burst Type 0 = sequential, 1 = interleaved
     MR[5-3]   burst length 001 = 2, 010 = 4, 011 = 8, others reserved
-    MR[0-2]   dont care 
+    MR[0-2]   dont care
 
-    CAS Latency 
+    CAS Latency
     000       reserved
     001       reserved
     010       2
@@ -498,10 +498,10 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 
 		// if everything verified then found low bond
 		break;
-		
+
 	}
-	print_val("\nLow Bond ",i);	
-	if( i < 0xff ){ 
+	print_val("\nLow Bond ",i);
+	if( i < 0xff ){
 		c = i++;
 		for(  ; i <0xff ; i++){
  			pci_write_config8(north,0x68,i ^ (i>>1) );
@@ -588,7 +588,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 
 
 	pci_write_config8(north,0x71,0xc8);
-	
+
 
 	/* graphics aperture base */
 
diff --git a/src/northbridge/via/vt8623/vga.c b/src/northbridge/via/vt8623/vga.c
index 7dbb7831b1..78ffe0aa94 100644
--- a/src/northbridge/via/vt8623/vga.c
+++ b/src/northbridge/via/vt8623/vga.c
@@ -57,7 +57,7 @@ static int via_vt8623_int15_handler(struct eregs *regs)
 	case 0x5f02:
 		regs->eax=0x5f;
 		regs->ebx= (regs->ebx & 0xffff0000) | 2;
-		regs->ecx= (regs->ecx & 0xffff0000) | 0x401;  // PAL + crt only 
+		regs->ecx= (regs->ecx & 0xffff0000) | 0x401;  // PAL + crt only
 		regs->edx= (regs->edx & 0xffff0000) | 0;  // TV Layout - default
 		res=0;
 		break;
@@ -65,7 +65,7 @@ static int via_vt8623_int15_handler(struct eregs *regs)
 		regs->eax=0x860f;
 		break;
         default:
-		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", 
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
 				regs->eax & 0xffff);
 		break;
 	}
@@ -122,11 +122,11 @@ static void vga_init(device_t dev)
 	//   call_bios_interrupt(0x10,0x4f1f,0x8003,1,0);
 	// this is how it looks:
 	vga_enable_console();
-	
+
 #ifdef MEASURE_VGA_INIT_TIME
 	clocks2 = rdmsr(0x10);
 	instructions = rdmsr(0xc2);
-	
+
 	printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
 	printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
 	printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c
index c3097cf2cb..172a8de148 100644
--- a/src/northbridge/via/vx800/dev_init.c
+++ b/src/northbridge/via/vx800/dev_init.c
@@ -30,8 +30,8 @@ CB_STATUS VerifyChc(void);
 
 /*===================================================================
 Function   : DRAMRegInitValue()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
@@ -68,7 +68,7 @@ static const u8 DramRegTbl[][3] = {
 	// {0x79, 0x00, 0x8F },
 	{0x85, 0x00, 0x00},
 	// {0x90, 0x87, 0x78 },
-	// {0x91, 0x00, 0x46 }, 
+	// {0x91, 0x00, 0x46 },
 	{0x40, 0x00, 0x00},
 
 	{0, 0, 0}
@@ -155,8 +155,8 @@ void DRAMRegInitValue(DRAM_SYS_ATTR *DramAttr)
 
 /*===================================================================
 Function   : DRAMInitializeProc()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
@@ -176,7 +176,7 @@ static BOOLEAN ChkForExistLowBank(void)
 	Address = (u32 *) 4;
 	*Address = EXIST_TEST_PATTERN;
 
-	// _asm {WBINVD}   
+	// _asm {WBINVD}
 	WaitMicroSec(100);
 	Address = (u32 *) 8;
 	data32 = *Address;
@@ -223,7 +223,7 @@ void DRAMInitializeProc(DRAM_SYS_ATTR *DramAttr)
 			SetEndingAddr(DramAttr, idx, 0x10); /* Assume 1G size */
 			if (idx < 4) /* CHA init */
 				InitDDR2CHA(DramAttr);	// temp wjb 2007/1 only for compiling
-			// in the function InitDDR2,the parameter is no need   
+			// in the function InitDDR2,the parameter is no need
 			Status = ChkForExistLowBank();
 			if (Status == TRUE) {
 				PRINT_DEBUG_MEM(" S\r");
@@ -247,8 +247,8 @@ void DRAMInitializeProc(DRAM_SYS_ATTR *DramAttr)
 
 /*===================================================================
 Function   : DRAMSetVRNUM()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 		  PhyRank:   Physical Rank number
@@ -285,14 +285,14 @@ void DRAMSetVRNum(DRAM_SYS_ATTR *DramAttr, u8 PhyRank /* physical rank */,
 
 /*===================================================================
 Function   : SetEndingAddr()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 		  VirRank:    Virtual Rank number
-		  Value:       (value) add or subtract value to this and after banks 
+		  Value:       (value) add or subtract value to this and after banks
 Output     : Void
-Purpose   : Set ending address of virtual rank specified by VirRank 
+Purpose   : Set ending address of virtual rank specified by VirRank
 ===================================================================*/
 
 void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank /* ending address
@@ -312,8 +312,8 @@ void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank /* ending address
 
 /*===================================================================
 Function   : InitDDR2()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
@@ -522,13 +522,13 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr)
 
 /*===================================================================
 Function   : InitDDR2_CHB()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
 Purpose   : Initialize DDR2 of CHB by standard sequence
-Reference  : 
+Reference  :
 ===================================================================*/
 /*//		                 DLL:	      Enable				  Reset
 static const  u32 CHB_MRS_DLL_150[2] =	{ 0x00020200 | (1 << 20), 0x00000800 };	// with 150 ohm (A17=1, A9=1), (A11=1)(cpu address)
@@ -569,7 +569,7 @@ void InitDDR2CHB(
 
     Data = 0x80;
     pci_write_config8(MEMCTRL, 0x54, Data);
-	
+
     // step3.
     //disable bank paging and multi page
     Data=pci_read_config8(MEMCTRL, 0x69);
@@ -579,18 +579,18 @@ void InitDDR2CHB(
     Data=pci_read_config8(MEMCTRL, 0xd3);
     Data |= 0x80;
     pci_write_config8(MEMCTRL, 0xd3, Data);
-	
+
     //step 4. Initialize CHB begin
     Data=pci_read_config8(MEMCTRL, 0xd3);
     Data |= 0x40;
     pci_write_config8(MEMCTRL, 0xd3, Data);
-	
+
     //Step 5. NOP command enable
     Data=pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
     Data  |= 0x08;
     pci_write_config8(MEMCTRL, 0xd7, Data);
-   
+
     //Step 6.  issue a nop cycle,RegD3[7]  0 -> 1
     Data=pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0x7F;
@@ -604,7 +604,7 @@ void InitDDR2CHB(
     // Loop 200us
     for (Idx = 0; Idx < 0x10; Idx++)
         WaitMicroSec(10);
-	
+
     // Step 8.
     // all banks precharge command enable
     Data=pci_read_config8(MEMCTRL, 0xd7);
@@ -618,7 +618,7 @@ void InitDDR2CHB(
     pci_write_config8(MEMCTRL, 0xd3, Data);
     Data |=  0x80;
     pci_write_config8(MEMCTRL, 0xd3, Data);
-	
+
    //step10. EMRS enable
     Data=pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
@@ -661,7 +661,7 @@ void InitDDR2CHB(
     Data |= 0x00;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
-    //step 14. MSR DLL Reset 
+    //step 14. MSR DLL Reset
     AccessAddr = CHB_MRS_DLL_150[1] >> 3;
     Data =(u8) (AccessAddr & 0xff);
     pci_write_config8(MEMCTRL, 0xd9, Data);
@@ -691,7 +691,7 @@ void InitDDR2CHB(
     Data |= 0x10;
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
-   
+
    // step17. issue precharge all cycle
     Data=pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0x7F;
@@ -718,7 +718,7 @@ void InitDDR2CHB(
 
     WaitMicroSec(200);
     }
-	
+
     //step22. MSR enable
     Data=pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
@@ -730,7 +730,7 @@ void InitDDR2CHB(
     Data |= 0x00;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
-  
+
     //the SDRAM parameters.(Burst Length, CAS# Latency , Write recovery etc.)
     //-------------------------------------------------------------
     //Burst Length : really offset Rx6c[1]
@@ -773,7 +773,7 @@ void InitDDR2CHB(
     pci_write_config8(MEMCTRL, 0xd3, Data);
     Data |=  0x80;
     pci_write_config8(MEMCTRL, 0xd3, Data);
-	
+
     //step 25. EMRS enable
     Data=pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
@@ -784,7 +784,7 @@ void InitDDR2CHB(
     Data &= 0xC7;
     Data |= 0x08;
     pci_write_config8(MEMCTRL, 0xd3, Data);
-	
+
 
     //step 26. OCD default
      AccessAddr = (CHB_OCD_Default_150ohm) >> 3;
@@ -805,7 +805,7 @@ void InitDDR2CHB(
     pci_write_config8(MEMCTRL, 0xd3, Data);
     Data |=  0x80;
     pci_write_config8(MEMCTRL, 0xd3, Data);
-	
+
      //step 25. EMRS enable
     Data=pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
@@ -859,12 +859,12 @@ void InitDDR2CHB(
     Data |= 0x00;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
-    //step 31.  exit the initialization mode 
+    //step 31.  exit the initialization mode
     Data=pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0xBF;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
-	
+
     //step 32. Enable bank paging and multi page
     Data=pci_read_config8(MEMCTRL, 0x69);
     Data |= 0x03;
@@ -874,13 +874,13 @@ void InitDDR2CHB(
 
 /*===================================================================
 Function   : InitDDR2CHC()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
 Purpose   : Initialize DDR2 of CHC by standard sequence
-Reference  : 
+Reference  :
 ===================================================================*/
 //                      DDR2                 CL=2          CL=3 CL=4   CL=5     (Burst type=interleave)(WR fine tune in code)
 static const u16 CHC_MRS_table[4] = { 0x22B, 0x23B, 0x24B, 0x25B };	// Use 1X-bandwidth MA table to init DRAM
@@ -1102,7 +1102,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr)
 	Status = VerifyChc();
 	if (Status != CB_SUCCESS)
 		PRINT_DEBUG_MEM("Error!!!!CHC init error!\r");
-	//step 31.  exit the initialization mode 
+	//step 31.  exit the initialization mode
 	Data = pci_read_config8(MEMCTRL, 0xdb);
 	Data &= 0x9F;
 	pci_write_config8(MEMCTRL, 0xdb, Data);
diff --git a/src/northbridge/via/vx800/dqs_search.c b/src/northbridge/via/vx800/dqs_search.c
index 785d775baf..c4971d1b17 100644
--- a/src/northbridge/via/vx800/dqs_search.c
+++ b/src/northbridge/via/vx800/dqs_search.c
@@ -22,8 +22,8 @@ void SetDQSOutputCHB(DRAM_SYS_ATTR * DramAttr);
 
 /*===================================================================
 Function   : DRAMDQSOutputSearchCHA()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
@@ -40,12 +40,12 @@ void DRAMDQSOutputSearch(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : SetDQSOutputCHA()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
-Purpose   :  according the frequence set CHA DQS output 
+Purpose   :  according the frequence set CHA DQS output
 ===================================================================*/
 void SetDQSOutputCHA(DRAM_SYS_ATTR * DramAttr)
 {
@@ -80,8 +80,8 @@ void SetDQSOutputCHA(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : DRAMDQSInputSearch()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
diff --git a/src/northbridge/via/vx800/dram_util.c b/src/northbridge/via/vx800/dram_util.c
index 342a6e0454..7688ab34a8 100644
--- a/src/northbridge/via/vx800/dram_util.c
+++ b/src/northbridge/via/vx800/dram_util.c
@@ -30,11 +30,11 @@ void WaitMicroSec(UINTN MicroSeconds)
 
 /*===================================================================
 Function   : via_write_phys()
-Precondition : 
+Precondition :
 Input      :  addr
                   value
 Output     : void
-Purpose    : 
+Purpose    :
 Reference  : None
 ===================================================================*/
 
@@ -47,10 +47,10 @@ void via_write_phys(volatile u32 addr, volatile u32 value)
 
 /*===================================================================
 Function   : via_read_phys()
-Precondition : 
+Precondition :
 Input      :  addr
-Output     : u32 
-Purpose    : 
+Output     : u32
+Purpose    :
 Reference  : None
 ===================================================================*/
 
@@ -63,10 +63,10 @@ u32 via_read_phys(volatile u32 addr)
 
 /*===================================================================
 Function   : DimmRead()
-Precondition : 
+Precondition :
 Input      :  x
-Output     : u32 
-Purpose    : 
+Output     : u32
+Purpose    :
 Reference  : None
 ===================================================================*/
 
@@ -80,13 +80,13 @@ u32 DimmRead(volatile u32 x)
 
 /*===================================================================
 Function   : DramBaseTest()
-Precondition : this function used to verify memory  
-Input      :  
+Precondition : this function used to verify memory
+Input      :
                  BaseAdd,
                  length,
                  mode
 Output     : u32
-Purpose    :write into and read out to verify if dram is correct 
+Purpose    :write into and read out to verify if dram is correct
 Reference  : None
 ===================================================================*/
 BOOLEAN DramBaseTest(u32 BaseAdd, u32 Length,
@@ -170,8 +170,8 @@ BOOLEAN DramBaseTest(u32 BaseAdd, u32 Length,
 
 /*===================================================================
 Function   : DumpRegisters()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
                 pPCIPPI,
                 DevNum,
                 FuncNum
@@ -209,8 +209,8 @@ void DumpRegisters(INTN DevNum, INTN FuncNum)
 
 /*===================================================================
 Function   : dumpnorth()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
                 pPCIPPI,
                 Func
 Output     : Void
diff --git a/src/northbridge/via/vx800/driving_setting.c b/src/northbridge/via/vx800/driving_setting.c
index c6a7edda05..bdba494d85 100644
--- a/src/northbridge/via/vx800/driving_setting.c
+++ b/src/northbridge/via/vx800/driving_setting.c
@@ -58,7 +58,7 @@ void DRAMDriving(DRAM_SYS_ATTR * DramAttr)
 /*
 ODT	Control	for DQ/DQS/CKE/SCMD/DCLKO in ChA & ChB
 which include driving enable/range and strong/weak selection
- 
+
 Processing: According to DRAM frequency to ODT control bits.
       		Because function enable bit must be the last one to be set.
       		So the register VIA_NB3DRAM_REGD4 and VIA_NB3DRAM_REGD3 should be
@@ -125,7 +125,7 @@ static const u8 ODTLookup_TBL[ODTLookup_Tbl_count][3] = {
 };
 
 #define ODT_Table_Width_DDR2		4
-//                                                                                               RxD6   RxD3 
+//                                                                                               RxD6   RxD3
 static const u8 ODT_Control_DDR2[ODT_Table_Width_DDR2] = { 0xFC, 0x01 };
 
 void DrivingODT(DRAM_SYS_ATTR * DramAttr)
diff --git a/src/northbridge/via/vx800/examples/driving_clk_phase_data.c b/src/northbridge/via/vx800/examples/driving_clk_phase_data.c
index a93c9a03c4..5e8e214d1f 100644
--- a/src/northbridge/via/vx800/examples/driving_clk_phase_data.c
+++ b/src/northbridge/via/vx800/examples/driving_clk_phase_data.c
@@ -20,7 +20,7 @@
 
  #include "northbridge/via/vx800/driving_clk_phase_data.h"
 
-// DQS	Driving  
+// DQS	Driving
 //Reg0xE0, 0xE1
 // According to #Bank to set DRAM DQS Driving
 //	                          #Bank	   1	 2     3     4	   5	 6     7     8
@@ -161,7 +161,7 @@ static const  u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM
         {0x8C,  0xFC,  0x03,  0x03,  0x03,  0x03 }
     };
 
-/*static const  u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = 
+/*static const  u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] =
     {
         //    (And NOT) DDR800 DDR667 DDR533 DDR400
         //Reg  Mask  Value Value Value Value
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index 8db60237b7..63755c3181 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -362,7 +362,7 @@ g)      Rx73h = 32h
 	/* decide if this is a s3 wakeup or a normal boot */
 	boot_mode = acpi_is_wakeup_early_via_vx800();
 	/*add this, to transfer "cpu restart" to "cold boot"
-	   When this boot is not a S3 resume, and PCI registers had been written, 
+	   When this boot is not a S3 resume, and PCI registers had been written,
 	   then this must be a cpu restart(result of os reboot cmd). so we need a real "cold boot". */
 	if ((boot_mode != 3)
 	    && (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) {
@@ -371,7 +371,7 @@ g)      Rx73h = 32h
 
 	/*x86 cold boot I/O cmd */
 	enable_smbus();
-	//smbus_fixup(&ctrl);// this fix does help vx800!, but vx855 no need this 
+	//smbus_fixup(&ctrl);// this fix does help vx800!, but vx855 no need this
 
 	if (bist == 0) {
 		// CAR need mtrr untill mem is ok, so i disable this early_mtrr_init();
@@ -441,7 +441,7 @@ g)      Rx73h = 32h
 
 	/*
 	   For coreboot most time of S3 resume is the same as normal boot, so some memory area under 1M become dirty,
-	   so before this happen, I need to backup the content of mem to top-mem. 
+	   so before this happen, I need to backup the content of mem to top-mem.
 	   I will reserve the 1M top-men in LBIO table in coreboot_table.c and recovery the content of 1M-mem in wakeup.c
 	 */
 #if PAYLOAD_IS_SEABIOS==1	//
@@ -449,7 +449,7 @@ g)      Rx73h = 32h
 		/*   some idea of Libo.Feng at amd.com in  http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html
 		   I want move the 1M data, I have to set some MTRRs myself. */
 		/* seting mtrr before back memoy save s3 resume time about 0.14 seconds */
-		/*because CAR stack use cache, and here to use cache , must be careful, 
+		/*because CAR stack use cache, and here to use cache , must be careful,
 		   1 during these mtrr code, must no function call, (after this mtrr, I think it should be ok to use function)
 		   2 before stack switch, no use variable that have value set before this
 		   3 due to 2, take care of "cpu_reset", I directlly set it to ZERO.
@@ -462,7 +462,7 @@ g)      Rx73h = 32h
 		u32 memtop4 =
 		    *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000 +
 		    0xe0000;
-		/*      __asm__ volatile (              
+		/*      __asm__ volatile (
 		   "movl    $0x204, %%ecx\n\t"
 		   "xorl    %%edx, %%edx\n\t"
 		   "movl     %0,%%eax\n\t"
@@ -478,7 +478,7 @@ g)      Rx73h = 32h
 		   "wrmsr\n\t"
 		   ::"g"(memtop2)
 		   );
-		   __asm__ volatile (           
+		   __asm__ volatile (
 		   "movl    $0x206, %%ecx\n\t"
 		   "xorl    %%edx, %%edx\n\t"
 		   "movl     %0,%%eax\n\t"
@@ -494,7 +494,7 @@ g)      Rx73h = 32h
 		   "wrmsr\n\t"
 		   ::"g"(memtop1)
 		   );
-		   __asm__ volatile (       
+		   __asm__ volatile (
 		   "movl    $0x208, %ecx\n\t"
 		   "xorl    %edx, %edx\n\t"
 		   "movl    $0,%eax\n\t"
@@ -512,21 +512,21 @@ g)      Rx73h = 32h
 		 */
 		// WAKE_MEM_INFO is  inited in get_set_top_available_mem in tables.c
 		// these two memcpy not not be enabled if set the MTRR around this two lines.
-		/*__asm__ volatile (		
+		/*__asm__ volatile (
 	 			"movl    $0, %%esi\n\t"
         "movl    %0, %%edi\n\t"
        	"movl    $0xa0000, %%ecx\n\t"
        	"shrl    $2, %%ecx\n\t"
-        "rep movsd\n\t"    
-        ::"g"(memtop3)        
+        "rep movsd\n\t"
+        ::"g"(memtop3)
    	);
-	__asm__ volatile (		
+	__asm__ volatile (
 	 			"movl    $0xe0000, %%esi\n\t"
         "movl    %0, %%edi\n\t"
        	"movl    $0x20000, %%ecx\n\t"
        	"shrl    $2, %%ecx\n\t"
-        "rep movsd\n\t"    
-        ::"g"(memtop4)        
+        "rep movsd\n\t"
+        ::"g"(memtop4)
    	);*/
 		print_debug("copy memory to high memory to protect s3 wakeup vector code \n");	//this can have function call, because no variable used before this
 		memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) -
@@ -537,22 +537,22 @@ g)      Rx73h = 32h
 		       (unsigned char *) 0xe0000, 0x20000);
 
 		/* restore the MTRR previously modified. */
-/*		__asm__ volatile (	
-        "wbinvd\n\t"     			
+/*		__asm__ volatile (
+        "wbinvd\n\t"
         "xorl    %edx, %edx\n\t"
        	"xorl    %eax, %eax\n\t"
        	"movl    $0x204, %ecx\n\t"
         "wrmsr\n\t"
-	 			"movl    $0x205, %ecx\n\t"                                      
-        "wrmsr\n\t"        
+	 			"movl    $0x205, %ecx\n\t"
+        "wrmsr\n\t"
 	 			"movl    $0x206, %ecx\n\t"
         "wrmsr\n\t"
-	 			"movl    $0x207, %ecx\n\t"                     
-        "wrmsr\n\t"        
-	 			"movl    $0x208, %ecx\n\t"                     
-        "wrmsr\n\t"        
-	 			"movl    $0x209, %ecx\n\t"                     
-        "wrmsr\n\t"        
+	 			"movl    $0x207, %ecx\n\t"
+        "wrmsr\n\t"
+	 			"movl    $0x208, %ecx\n\t"
+        "wrmsr\n\t"
+	 			"movl    $0x209, %ecx\n\t"
+        "wrmsr\n\t"
 		);*/
 	}
 #endif
diff --git a/src/northbridge/via/vx800/final_setting.c b/src/northbridge/via/vx800/final_setting.c
index 97cc21820a..9ec31b58da 100644
--- a/src/northbridge/via/vx800/final_setting.c
+++ b/src/northbridge/via/vx800/final_setting.c
@@ -64,8 +64,8 @@ void DRAMRefreshCounter(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : DRAMRegFinalValue()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c
index 47a99c3cc1..03daeec342 100644
--- a/src/northbridge/via/vx800/freq_setting.c
+++ b/src/northbridge/via/vx800/freq_setting.c
@@ -230,7 +230,7 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr)
 		DramAttr->DramFreq = DIMMFREQ_200;
 		DramAttr->DramCyc = 1000;
 	}
-	//if set the frequence mannul                
+	//if set the frequence mannul
 	PRINT_DEBUG_MEM("Dram Frequency:");
 	PRINT_DEBUG_MEM_HEX16(DramAttr->DramFreq);
 	PRINT_DEBUG_MEM(" \r");
diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c
index 4dfe843bae..37e559c026 100644
--- a/src/northbridge/via/vx800/northbridge.c
+++ b/src/northbridge/via/vx800/northbridge.c
@@ -118,7 +118,7 @@ static u32 find_pci_tolm(struct bus *bus)
 
 static void pci_domain_set_resources(device_t dev)
 {
-	/* 
+	/*
 	 * the order is important to find the correct ram size.
 	 */
 	u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
diff --git a/src/northbridge/via/vx800/rank_map.c b/src/northbridge/via/vx800/rank_map.c
index 6c88c68953..3eada63329 100644
--- a/src/northbridge/via/vx800/rank_map.c
+++ b/src/northbridge/via/vx800/rank_map.c
@@ -32,8 +32,8 @@ void DRAMPRToVRMapping(DRAM_SYS_ATTR * DramAttr);
 
 /*===================================================================
 Function   : DRAMBankInterleave()
-Precondition : 
-Input        : 
+Precondition :
+Input        :
 		   DramAttr: pointer point to  DRAMSYSATTR  which consist the DDR and Dimm information in MotherBoard
 Output     :  Void
 Purpose   :  STEP 13 Set Bank Interleave  VIANB3DRAMREG69[7:6] 00:No Interleave 01:2 Bank 10:4 Bank	11:8 Bank
@@ -85,11 +85,11 @@ void DRAMBankInterleave(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : DRAMSizingMATypeM()
-Precondition : 
+Precondition :
 Input        :
 		   DramAttr: pointer point to  DRAMSYSATTR  which consist the DDR and Dimm information in MotherBoard
 Output     :  Void
- Purpose  : STEP 14  1 DRAM Sizing 2  Fill MA type 3 Prank to vrankMapping 
+ Purpose  : STEP 14  1 DRAM Sizing 2  Fill MA type 3 Prank to vrankMapping
 ===================================================================*/
 void DRAMSizingMATypeM(DRAM_SYS_ATTR * DramAttr)
 {
@@ -103,8 +103,8 @@ void DRAMSizingMATypeM(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : DRAMClearEndingAddress()
-Precondition : 
-Input        : 
+Precondition :
+Input        :
 		   DramAttr: pointer point to  DRAMSYSATTR  which consist the DDR and Dimm information in MotherBoard
 Output     : Void
 Purpose   : clear Ending and Start adress from 0x40-4f to zero
@@ -120,8 +120,8 @@ void DRAMClearEndingAddress(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : DRAMSizingEachRank()
-Precondition : 
-Input        : 
+Precondition :
+Input        :
 		   DramAttr: pointer point to  DRAMSYSATTR  which consist the DDR and Dimm information in MotherBoard
 Output     : Void
 Purpose   : Sizing each Rank invidually, by number of rows column banks pins, be care about 128bit
@@ -189,8 +189,8 @@ void DRAMSizingEachRank(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : DRAMSetRankMAType()
-Precondition : 
-Input       : 
+Precondition :
+Input       :
 		  DramAttr: pointer point to  DRAMSYSATTR  which consist the DDR and Dimm information in MotherBoard
 Output     : Void
 Purpose   : set the matype Reg by MAMapTypeTbl, which the rule can be found in memoryinit
@@ -258,11 +258,11 @@ void DRAMSetRankMAType(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : DRAMSetEndingAddress()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		  DramAttr: pointer point to  DRAMSYSATTR  which consist the DDR and Dimm information in MotherBoard
 Output     : Void
-Purpose   : realize the Vrank 40...Reg (Start and Ending Regs). Vrank have  same order with phy Rank, Size is actual Size  
+Purpose   : realize the Vrank 40...Reg (Start and Ending Regs). Vrank have  same order with phy Rank, Size is actual Size
 ===================================================================*/
 void DRAMSetEndingAddress(DRAM_SYS_ATTR * DramAttr)
 {
@@ -311,8 +311,8 @@ void DRAMSetEndingAddress(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : DRAMPRToVRMapping()
-Precondition : 
-Input       : 
+Precondition :
+Input       :
 		  DramAttr: pointer point to  DRAMSYSATTR  which consist the DDR and Dimm information in MotherBoard
 Output     : Void
 Purpose   : set the Vrank-prank map with the same order
diff --git a/src/northbridge/via/vx800/timing_setting.c b/src/northbridge/via/vx800/timing_setting.c
index a1d8e74812..7668b22e0b 100644
--- a/src/northbridge/via/vx800/timing_setting.c
+++ b/src/northbridge/via/vx800/timing_setting.c
@@ -72,7 +72,7 @@ void DRAMTimingSetting(DRAM_SYS_ATTR * DramAttr)
 
 /*
 Set DRAM Timing: CAS Latency for DDR1
-D0F3RX62 bit[0:2] for CAS Latency; 
+D0F3RX62 bit[0:2] for CAS Latency;
 */
 void SetCL(DRAM_SYS_ATTR * DramAttr)
 {
diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c
index 72420981ff..6fe8194922 100644
--- a/src/northbridge/via/vx800/uma_ram_setting.c
+++ b/src/northbridge/via/vx800/uma_ram_setting.c
@@ -139,7 +139,7 @@ void SetUMARam(void)
 
 //      vga_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VGA, 0);
 
-	//RxB2 may be for S.L. and RxB1 may be for L. L. 
+	//RxB2 may be for S.L. and RxB1 may be for L. L.
 	// It is different from Spec.
 	ByteVal = SLD1F0Val;
 	pci_write_config8(vga_dev, 0xb2, ByteVal);
@@ -256,7 +256,7 @@ void SetUMARam(void)
 	}
 	outb(ByteVal, 0x03d5);
 
-	// Set frame buffer size 
+	// Set frame buffer size
 	outb(0x39, 0x03c4);
 	outb(1 << SLD0F3Val, 0x03c5);
 
@@ -295,7 +295,7 @@ void SetUMARam(void)
 	SLBase = (RamSize << 26) - (UmaSize << 20);
 
 	outb(0x6D, 0x03c4);
-	//SL Base[28:21] 
+	//SL Base[28:21]
 	outb((u8) ((SLBase >> 21) & 0xFF), 0x03c5);
 
 	outb(0x6e, 0x03c4);
diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c
index 3897e010b5..7bdc3418f1 100644
--- a/src/northbridge/via/vx800/vga.c
+++ b/src/northbridge/via/vx800/vga.c
@@ -62,19 +62,19 @@ static int via_vx800_int15_handler(struct eregs *regs)
 	case 0x5f18:
 	{
 		/*
-		 * BL Bit[7:4] 
-		 * Memory Data Rate 
-		 * 0000: 66MHz 
-		 * 0001: 100MHz 
-		 * 0010: 133MHz 
-		 * 0011: 200MHz ( DDR200 ) 
-		 * 0100: 266MHz ( DDR266 ) 
-		 * 0101: 333MHz ( DDR333 ) 
-		 * 0110: 400MHz ( DDR400 ) 
-		 * 0111: 533MHz ( DDR I/II 533 
+		 * BL Bit[7:4]
+		 * Memory Data Rate
+		 * 0000: 66MHz
+		 * 0001: 100MHz
+		 * 0010: 133MHz
+		 * 0011: 200MHz ( DDR200 )
+		 * 0100: 266MHz ( DDR266 )
+		 * 0101: 333MHz ( DDR333 )
+		 * 0110: 400MHz ( DDR400 )
+		 * 0111: 533MHz ( DDR I/II 533
 		 * 1000: 667MHz ( DDR I/II 667)
-		 * Bit[3:0]  
-		 * N:  Frame Buffer Size 2^N  MB 
+		 * Bit[3:0]
+		 * N:  Frame Buffer Size 2^N  MB
 		 */
 		u8 i;
 		device_t dev;
@@ -109,7 +109,7 @@ static int via_vx800_int15_handler(struct eregs *regs)
 	case 0x5f02:
 		regs->eax=0x5f;
 		regs->ebx= (regs->ebx & 0xffff0000) | 2;
-		regs->ecx= (regs->ecx & 0xffff0000) | 0x401;  // PAL + crt only 
+		regs->ecx= (regs->ecx & 0xffff0000) | 0x401;  // PAL + crt only
 		regs->edx= (regs->edx & 0xffff0000) | 0;  // TV Layout - default
 		res=0;
 		break;
@@ -118,7 +118,7 @@ static int via_vx800_int15_handler(struct eregs *regs)
 		res = 0;
 		break;
         default:
-		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", 
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
 				regs->eax & 0xffff);
 		regs->eax = 0;
 		break;
diff --git a/src/northbridge/via/vx800/vx800_early_serial.c b/src/northbridge/via/vx800/vx800_early_serial.c
index 6462a2d295..8bac43ff12 100644
--- a/src/northbridge/via/vx800/vx800_early_serial.c
+++ b/src/northbridge/via/vx800/vx800_early_serial.c
@@ -70,7 +70,7 @@ static void enable_vx800_serial(void)
 	// turn on pnp
 	vx800_writepnpaddr(0x87);
 	vx800_writepnpaddr(0x87);
-	// now go ahead and set up com1. 
+	// now go ahead and set up com1.
 	// set address
 	vx800_writepnpaddr(0x7);
 	vx800_writepnpdata(0x2);
diff --git a/src/northbridge/via/vx800/vx800_early_smbus.c b/src/northbridge/via/vx800/vx800_early_smbus.c
index 7ba9b41acb..e40d54d721 100644
--- a/src/northbridge/via/vx800/vx800_early_smbus.c
+++ b/src/northbridge/via/vx800/vx800_early_smbus.c
@@ -171,10 +171,10 @@ static void enable_smbus(void)
 }
 
 /**
- * A fixup for some systems that need time for the SMBus to "warm up". This is 
- * needed on some VT823x based systems, where the SMBus spurts out bad data for 
- * a short time after power on. This has been seen on the VIA Epia series and 
- * Jetway J7F2-series. It reads the ID byte from SMBus, looking for 
+ * A fixup for some systems that need time for the SMBus to "warm up". This is
+ * needed on some VT823x based systems, where the SMBus spurts out bad data for
+ * a short time after power on. This has been seen on the VIA Epia series and
+ * Jetway J7F2-series. It reads the ID byte from SMBus, looking for
  * known-good data from a slot/address. Exits on either good data or a timeout.
  *
  * TODO: This should probably go into some global file, but one would need to
diff --git a/src/northbridge/via/vx800/vx800_lpc.c b/src/northbridge/via/vx800/vx800_lpc.c
index 874f32fbbd..ce2d822946 100644
--- a/src/northbridge/via/vx800/vx800_lpc.c
+++ b/src/northbridge/via/vx800/vx800_lpc.c
@@ -42,9 +42,9 @@ static const unsigned char sd_ms_ctrl_Pins[4] = { 'B', 'C', 'D', 'A' };	//only I
 static const unsigned char ce_ata_nf_ctrl_Pins[4] = { 'C', 'C', 'D', 'A' };	//only INTA
 static const unsigned char idePins[4] = { 'B', 'C', 'D', 'A' };	//only INTA
 
-static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' };	//all 4 
+static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' };	//all 4
 
-static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' };	//only INTA 
+static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' };	//only INTA
 
 static unsigned char *pin_to_irq(const unsigned char *pin)
 {
@@ -218,7 +218,7 @@ static void S3_ps2_kb_ms_wakeup(struct device *dev)
 	pci_write_config8(dev, 0x51, enables);
 
 	outb(inb(VX800_ACPI_IO_BASE + 0x02) | 0x20, VX800_ACPI_IO_BASE + 0x02);	//ACPI golabe enable for sci smi trigger
-	outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x204, VX800_ACPI_IO_BASE + 0x22);	//ACPI SCI on Internal KBC PME and mouse PME  
+	outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x204, VX800_ACPI_IO_BASE + 0x22);	//ACPI SCI on Internal KBC PME and mouse PME
 
 }
 
@@ -354,17 +354,17 @@ static void southbridge_init(struct device *dev)
 		fadt->pm2_cnt_len = 1;//to support cpu-c3
 	#2
 		ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC )
-       #3    write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec. 
+       #3    write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec.
 	       1  enable SLP# asserts in C3 state  PMIORx26<1> =1
 		2    enable CPUSTP# asserts in C3 state;  PMIORx26<2> =1
 		3  CLKRUN# is always asserted  PMIORx26<3> =0
-		4    Disable PCISTP# When CLKRUN# is asserted 
-		1: PCISTP# will not assert When CLKRUN# is asserted 
+		4    Disable PCISTP# When CLKRUN# is asserted
+		1: PCISTP# will not assert When CLKRUN# is asserted
 		PMIORx26<4> =1
-		5  This bit controls whether the CPU voltage is lowered when in C3/S1 state.     
-		VRDSLP will be active in either this bit set in C3 or LVL4 register read 
+		5  This bit controls whether the CPU voltage is lowered when in C3/S1 state.
+		VRDSLP will be active in either this bit set in C3 or LVL4 register read
 		PMIORx26<0> =0
-		6  Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state  PMIORx15 
+		6  Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state  PMIORx15
 	*/
 	outb(0x17, VX800_ACPI_IO_BASE + 0x26);