x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer

On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)

5 files changed, 90 insertions, 90 deletions

diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index 747cbfd922..289b315158 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -393,7 +393,7 @@ static void sdram_set_post(const struct mem_controller *ctrl)
 	pci_write_config16(dev, 0xa4, 0x0010);
 }
 
-static void sdram_enable(device_t dev, unsigned long rank_address)
+static void sdram_enable(device_t dev, u8 *rank_address)
 {
 	u8 i;
 
@@ -413,7 +413,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
 	PRINT_DEBUG_MEM("RAM Enable 3: Mode register set\n");
 	do_ram_command(dev, RAM_COMMAND_MRS);
 	read32(rank_address + 0x120000);	/* EMRS DLL Enable */
-	read32(rank_address + 0x800);		/* MRS DLL Reset */
+	read32(rank_address + 0x800);	/* MRS DLL Reset */
 
 	/* 4. Precharge all again. */
 	PRINT_DEBUG_MEM("RAM Enable 4: Precharge all\n");
@@ -457,10 +457,10 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 	c7_cpu_setup(ctrl->d0f2);
 	sdram_set_registers(ctrl);
 	sdram_set_size(ctrl);
-	sdram_enable(ctrl->d0f3, 0);
+	sdram_enable(ctrl->d0f3, (u8 *)0);
 	reg = pci_read_config8(ctrl->d0f3, 0x41);
 	if (reg != 0)
 		sdram_enable(ctrl->d0f3,
-			     pci_read_config8(ctrl->d0f3, 0x40) << 26);
+			     (u8 *)(pci_read_config8(ctrl->d0f3, 0x40) << 26));
 	sdram_set_post(ctrl);
 }
diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c
index 1e6d2ce47d..56842b094c 100644
--- a/src/northbridge/via/cx700/lpc.c
+++ b/src/northbridge/via/cx700/lpc.c
@@ -274,7 +274,7 @@ static void cx700_lpc_init(struct device *dev)
 
 #if CONFIG_IOAPIC
 #define IO_APIC_ID 2
-	setup_ioapic(IO_APIC_ADDR, IO_APIC_ID);
+	setup_ioapic(VIO_APIC_VADDR, IO_APIC_ID);
 #endif
 
 	/* Initialize interrupts */
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index 32be1ea4cd..fabd7ffb31 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -967,9 +967,9 @@ static void step_20_21(const struct mem_controller *ctrl)
 
 	val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
 	if (val & DDR2_ODT_150ohm)
-		read32(0x102200);
+		read32((void *)0x102200);
 	else
-		read32(0x102020);
+		read32((void *)0x102020);
 
 	/* Step 21. Normal operation */
 	printk(BIOS_SPEW, "RAM Enable 5: Normal operation\n");
@@ -995,7 +995,7 @@ static void step_2_19(const struct mem_controller *ctrl)
 
 	// Step 4
 	printk(BIOS_SPEW, "SEND: ");
-	read32(0);
+	read32((void *)0);
 	printk(BIOS_SPEW, "OK\n");
 
 	// Step 5
@@ -1007,7 +1007,7 @@ static void step_2_19(const struct mem_controller *ctrl)
 
 	// Step 7
 	printk(BIOS_SPEW, "SEND: ");
-	read32(0);
+	read32((void *)0);
 	printk(BIOS_SPEW, "OK\n");
 
 	/* Step 8. Mode register set. */
@@ -1019,14 +1019,14 @@ static void step_2_19(const struct mem_controller *ctrl)
 
 	val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
 	if (val & DDR2_ODT_150ohm)
-		read32(0x102200);	//DDR2_ODT_150ohm
+		read32((void *)0x102200);	//DDR2_ODT_150ohm
 	else
-		read32(0x102020);
+		read32((void *)0x102020);
 	printk(BIOS_SPEW, "OK\n");
 
 	// Step 10
 	printk(BIOS_SPEW, "SEND: ");
-	read32(0x800);
+	read32((void *)0x800);
 	printk(BIOS_SPEW, "OK\n");
 
 	/* Step 11. Precharge all. Wait tRP. */
@@ -1035,7 +1035,7 @@ static void step_2_19(const struct mem_controller *ctrl)
 
 	// Step 12
 	printk(BIOS_SPEW, "SEND: ");
-	read32(0x0);
+	read32((u32 *)0x0);
 	printk(BIOS_SPEW, "OK\n");
 
 	/* Step 13. Perform 8 refresh cycles. Wait tRC each time. */
@@ -1046,7 +1046,7 @@ static void step_2_19(const struct mem_controller *ctrl)
 	// Step 16: Repeat Step 14 and 15 another 7 times
 	for (i = 0; i < 8; i++) {
 		// Step 14
-		read32(0);
+		read32((u32 *)0);
 		printk(BIOS_SPEW, ".");
 
 		// Step 15
@@ -1076,7 +1076,7 @@ static void step_2_19(const struct mem_controller *ctrl)
 	val = pci_read_config8(MEMCTRL, 0x61);
 	val = val >> 6;
 	i |= DDR2_Twr_table[val];
-	read32(i);
+	read32((void *)i);
 
 	printk(BIOS_DEBUG, "MRS = %08x\n", i);
 
@@ -1085,9 +1085,9 @@ static void step_2_19(const struct mem_controller *ctrl)
 	// Step 19
 	val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
 	if (val & DDR2_ODT_150ohm)
-		read32(0x103e00);	//EMRS OCD Default
+		read32((void *)0x103e00);	//EMRS OCD Default
 	else
-		read32(0x103c20);
+		read32((void *)0x103c20);
 }
 
 static void sdram_set_vr(const struct mem_controller *ctrl, u8 num)
@@ -1133,45 +1133,45 @@ static void sdram_calc_size(const struct mem_controller *ctrl, u8 num)
 	u8 ca, ra, ba, reg;
 	ba = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_FLAGS);
 	if (ba == 8) {
-		write8(0, 0x0d);
-		ra = read8(0);
-		write8((1 << SDRAM1X_RA_12_8bk), 0x0c);
-		ra = read8(0);
-
-		write8(0, 0x0a);
-		ca = read8(0);
-		write8((1 << SDRAM1X_CA_09_8bk), 0x0c);
-		ca = read8(0);
-
-		write8(0, 0x03);
-		ba = read8(0);
-		write8((1 << SDRAM1X_BA2_8bk), 0x02);
-		ba = read8(0);
-		write8((1 << SDRAM1X_BA1_8bk), 0x01);
-		ba = read8(0);
+		write8((void *)0, 0x0d);
+		ra = read8((void *)0);
+		write8((void *)(1 << SDRAM1X_RA_12_8bk), 0x0c);
+		ra = read8((void *)0);
+
+		write8((void *)0, 0x0a);
+		ca = read8((void *)0);
+		write8((void *)(1 << SDRAM1X_CA_09_8bk), 0x0c);
+		ca = read8((void *)0);
+
+		write8((void *)0, 0x03);
+		ba = read8((void *)0);
+		write8((void *)(1 << SDRAM1X_BA2_8bk), 0x02);
+		ba = read8((void *)0);
+		write8((void *)(1 << SDRAM1X_BA1_8bk), 0x01);
+		ba = read8((void *)0);
 	} else {
-		write8(0, 0x0f);
-		ra = read8(0);
-		write8((1 << SDRAM1X_RA_14), 0x0e);
-		ra = read8(0);
-		write8((1 << SDRAM1X_RA_13), 0x0d);
-		ra = read8(0);
-		write8((1 << SDRAM1X_RA_12), 0x0c);
-		ra = read8(0);
-
-		write8(0, 0x0c);
-		ca = read8(0);
-		write8((1 << SDRAM1X_CA_12), 0x0b);
-		ca = read8(0);
-		write8((1 << SDRAM1X_CA_11), 0x0a);
-		ca = read8(0);
-		write8((1 << SDRAM1X_CA_09), 0x09);
-		ca = read8(0);
-
-		write8(0, 0x02);
-		ba = read8(0);
-		write8((1 << SDRAM1X_BA1), 0x01);
-		ba = read8(0);
+		write8((void *)0, 0x0f);
+		ra = read8((void *)0);
+		write8((void *)(1 << SDRAM1X_RA_14), 0x0e);
+		ra = read8((void *)0);
+		write8((void *)(1 << SDRAM1X_RA_13), 0x0d);
+		ra = read8((void *)0);
+		write8((void *)(1 << SDRAM1X_RA_12), 0x0c);
+		ra = read8((void *)0);
+
+		write8((void *)0, 0x0c);
+		ca = read8((void *)0);
+		write8((void *)(1 << SDRAM1X_CA_12), 0x0b);
+		ca = read8((void *)0);
+		write8((void *)(1 << SDRAM1X_CA_11), 0x0a);
+		ca = read8((void *)0);
+		write8((void *)(1 << SDRAM1X_CA_09), 0x09);
+		ca = read8((void *)0);
+
+		write8((void *)0, 0x02);
+		ba = read8((void *)0);
+		write8((void *)(1 << SDRAM1X_BA1), 0x01);
+		ba = read8((void *)0);
 	}
 
 	if (ra < 10 || ra > 15)
@@ -1277,19 +1277,19 @@ static void sdram_enable(const struct mem_controller *ctrl)
 			if (reg8) {
 				sdram_set_vr(ctrl, i);
 				sdram_ending_addr(ctrl, i);
-				write32(0, 0x55555555);
-				write32(4, 0x55555555);
+				write32((void *)0, 0x55555555);
+				write32((void *)4, 0x55555555);
 				udelay(15);
-				if (read32(0) != 0x55555555)
+				if (read32((void *)0) != 0x55555555)
 					break;
-				if (read32(4) != 0x55555555)
+				if (read32((void *)4) != 0x55555555)
 					break;
-				write32(0, 0xaaaaaaaa);
-				write32(4, 0xaaaaaaaa);
+				write32((void *)0, 0xaaaaaaaa);
+				write32((void *)4, 0xaaaaaaaa);
 				udelay(15);
-				if (read32(0) != 0xaaaaaaaa)
+				if (read32((void *)0) != 0xaaaaaaaa)
 					break;
-				if (read32(4) != 0xaaaaaaaa)
+				if (read32((void *)4) != 0xaaaaaaaa)
 					break;
 				sdram_clear_vr_addr(ctrl, i);
 			}
@@ -1310,19 +1310,19 @@ static void sdram_enable(const struct mem_controller *ctrl)
 				sdram_set_vr(ctrl, i);
 				sdram_ending_addr(ctrl, i);
 
-				write32(0, 0x55555555);
-				write32(4, 0x55555555);
+				write32((void *)0, 0x55555555);
+				write32((void *)4, 0x55555555);
 				udelay(15);
-				if (read32(0) != 0x55555555)
+				if (read32((void *)0) != 0x55555555)
 					break;
-				if (read32(4) != 0x55555555)
+				if (read32((void *)4) != 0x55555555)
 					break;
-				write32(0, 0xaaaaaaaa);
-				write32(4, 0xaaaaaaaa);
+				write32((void *)0, 0xaaaaaaaa);
+				write32((void *)4, 0xaaaaaaaa);
 				udelay(15);
-				if (read32(0) != 0xaaaaaaaa)
+				if (read32((void *)0) != 0xaaaaaaaa)
 					break;
-				if (read32(4) != 0xaaaaaaaa)
+				if (read32((void *)4) != 0xaaaaaaaa)
 					break;
 				sdram_clear_vr_addr(ctrl, i);
 			}
@@ -1364,17 +1364,17 @@ static void sdram_enable(const struct mem_controller *ctrl)
 			sdram_set_vr(ctrl, i);
 			sdram_ending_addr(ctrl, i);
 			if (reg8 == 4) {
-				write8(0, 0x02);
-				val = read8(0);
-				write8((1 << SDRAM1X_BA1), 0x01);
-				val = read8(0);
+				write8((void *)0, 0x02);
+				val = read8((void *)0);
+				write8((void *)(1 << SDRAM1X_BA1), 0x01);
+				val = read8((void *)0);
 			} else {
-				write8(0, 0x03);
-				val = read8(0);
-				write8((1 << SDRAM1X_BA2_8bk), 0x02);
-				val = read8(0);
-				write8((1 << SDRAM1X_BA1_8bk), 0x01);
-				val = read8(0);
+				write8((void *)0, 0x03);
+				val = read8((void *)0);
+				write8((void *)(1 << SDRAM1X_BA2_8bk), 0x02);
+				val = read8((void *)0);
+				write8((void *)(1 << SDRAM1X_BA1_8bk), 0x01);
+				val = read8((void *)0);
 			}
 			if (val < dl)
 				dl = val;
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c
index 3cff6b0bf6..61a8a7b96a 100644
--- a/src/northbridge/via/vx900/lpc.c
+++ b/src/northbridge/via/vx900/lpc.c
@@ -139,10 +139,10 @@ static void vx900_lpc_ioapic_setup(device_t dev)
 	/* The base address of this IOAPIC _must_ be at 0xfec00000.
 	 * Don't move this value to a #define, as people might think it's
 	 * configurable. It is not. */
-	const u32 base = config->base;
-	if (base != 0xfec00000) {
+	const void *base = config->base;
+	if (base != (void *)0xfec00000) {
 		printk(BIOS_ERR, "ERROR: South module IOAPIC base should be at "
-		       "0xfec00000\n but we found it at 0x%.8x\n", base);
+		       "0xfec00000\n but we found it at %p\n", base);
 		return;
 	}
 
diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c
index 5183391c76..fb151935b2 100644
--- a/src/northbridge/via/vx900/traf_ctrl.c
+++ b/src/northbridge/via/vx900/traf_ctrl.c
@@ -80,24 +80,24 @@ static void vx900_north_ioapic_setup(device_t dev)
 	 *     be between 0xfec00000 and 0xfecfff00
 	 *     be 256-byte aligned
 	 */
-	if ((config->base < 0xfec0000 || config->base > 0xfecfff00)
-	    || ((config->base & 0xff) != 0)) {
+	if ((config->base < (void *)0xfec0000 || config->base > (void *)0xfecfff00)
+	    || (((uintptr_t)config->base & 0xff) != 0)) {
 		printk(BIOS_ERR, "ERROR: North module IOAPIC base should be "
 		       "between 0xfec00000 and 0xfecfff00\n"
 		       "and must be aligned to a 256-byte boundary, "
-		       "but we found it at 0x%.8x\n", config->base);
+		       "but we found it at 0x%p\n", config->base);
 		return;
 	}
 
 	printk(BIOS_DEBUG, "VX900 TRAF_CTR: Setting up the north module IOAPIC "
-	       "at 0%.8x\n", config->base);
+	       "at %p\n", config->base);
 
 	/* First register of the IOAPIC base */
-	base_val = (config->base >> 8) & 0xff;
+	base_val = (((uintptr_t)config->base) >> 8) & 0xff;
 	pci_write_config8(dev, 0x41, base_val);
 	/* Second register of the base.
 	 * Bit[7] also enables the IOAPIC and bit[5] enables MSI cycles */
-	base_val = (config->base >> 16) & 0xf;
+	base_val = (((uintptr_t)config->base) >> 16) & 0xf;
 	pci_mod_config8(dev, 0x40, 0, base_val | (1 << 7) | (1 << 5));
 }