Some more DIMM0 related cleanups and deduplication.

 - VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do.

 - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of
   romstage.c files and lots of spd_addr.h files. Don't even bother for
   those spd_addr.h which aren't even actually used, drop them right away.

 - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1,
   and 0xa0 with (DIMM0 << 1) where appropriate.

 - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0,
   SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC.

 - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines.

 - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do.
   Then, replace 0xa0 (which now becomes 0x50) with DIMM0.

 - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes.

 - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 55 insertions, 63 deletions

diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c
index 7081c78744..23a6209458 100644
--- a/src/northbridge/via/cn400/raminit.c
+++ b/src/northbridge/via/cn400/raminit.c
@@ -174,17 +174,15 @@ static void ddr_ram_setup(void)
     Read SPD byte 17, Number of banks on SDRAM device.
 */
 	c = 0;
-	b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM);
+	b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM);
 	//print_val("Detecting Memory\nNumber of Banks ",b);
 
 	// Only supporting 4 bank chips just now
 	if( b == 4 ){
-		/*
-    		Read SPD byte 3, Number of row addresses.
-		*/
+		/* Read SPD byte 3, Number of row addresses. */
 		c = 0x01;
 		bank = 0x40;
-		b = smbus_read_byte(0x50, SPD_NUM_ROWS);
+		b = smbus_read_byte(DIMM0, SPD_NUM_ROWS);
 		//print_val("\nNumber of Rows ", b);
 
 		if( b >= 0x0d ){	// 256/512Mb
@@ -194,19 +192,15 @@ static void ddr_ram_setup(void)
 			else
 				bank = 0x44;
 
-			/*
-    			Read SPD byte 13, Primary DRAM width.
-			*/
-			b = smbus_read_byte(0x50, SPD_PRIMARY_SDRAM_WIDTH);
+			/* Read SPD byte 13, Primary DRAM width. */
+			b = smbus_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH);
 			//print_val("\nPrimary DRAM width", b);
 			if( b != 4 )   // not 64/128Mb (x4)
 				c = 0x81;  // 256Mb
 		}
 
-		/*
-    		Read SPD byte 4, Number of column addresses.
-		*/
-		b = smbus_read_byte(0x50, SPD_NUM_COLUMNS);
+		/* Read SPD byte 4, Number of column addresses. */
+		b = smbus_read_byte(DIMM0, SPD_NUM_COLUMNS);
 		//print_val("\nNo Columns ",b);
 		if( b == 10 || b == 11 || b == 12) c |= 0x60;   // 10/11 bit col addr
 		if( b == 9 ) c |= 0x40;           // 9 bit col addr
@@ -238,7 +232,7 @@ static void ddr_ram_setup(void)
 
 	// Read SPD byte 31 Module bank density
 	//c = 0;
-	b = smbus_read_byte(0x50, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
+	b = smbus_read_byte(DIMM0, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
 	if( b & 0x02 )
 	{
 		c = 0x40;         				// 2GB
@@ -278,7 +272,7 @@ static void ddr_ram_setup(void)
 	pci_write_config8(ctrl.d0f3, 0x40, c);
 
 	// SPD byte 5  # of physical banks
-	b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS);
+	b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS);
 
 	//print_val("\nNo Physical Banks ",b);
 	if( b == 2)
@@ -307,7 +301,7 @@ static void ddr_ram_setup(void)
 	ma = bank;
 
 	/* Read SPD byte 18 CAS Latency */
-	b = smbus_read_byte(0x50, SPD_ACCEPTABLE_CAS_LATENCIES);
+	b = smbus_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES);
 /*	print_debug("\nCAS Supported ");
 	if(b & 0x04)
 		print_debug("2 ");
@@ -316,30 +310,30 @@ static void ddr_ram_setup(void)
 	if(b & 0x10)
 		print_debug("3");
 
-	c = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
+	c = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 	print_val("\nCycle time at CL X     (nS)", c);
-	c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND);
+	c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND);
 	print_val("\nCycle time at CL X-0.5 (nS)", c);
-	c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD);
+	c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD);
 	print_val("\nCycle time at CL X-1   (nS)", c);
 */
 	/* Scaling of Cycle Time SPD data */
 	/* 7      4 3       0             */
 	/*    ns     x0.1ns               */
-	bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
+	bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 
 	if( b & 0x10 ){             // DDR offering optional CAS 3
 		//print_debug("\nStarting at CAS 3");
 		c = 0x30;
 		/* see if we can better it */
 		if( b & 0x08 ){     // DDR mandatory CAS 2.5
-			if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5
+			if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5
 				//print_debug("\nWe can do CAS 2.5");
 				c = 0x20;
 			}
 		}
 		if( b & 0x04 ){     // DDR mandatory CAS 2
-			if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
+			if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
 				//print_debug("\nWe can do CAS 2");
 				c = 0x10;
 			}
@@ -348,7 +342,7 @@ static void ddr_ram_setup(void)
 		//print_debug("\nStarting at CAS 2.5");
 		c = 0x20;          // assume CAS 2.5
 		if( b & 0x04){      // Should always happen
-			if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
+			if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
 				//print_debug("\nWe can do CAS 2");
 				c = 0x10;
 			}
@@ -383,7 +377,7 @@ static void ddr_ram_setup(void)
     Read SPD byte 27, min row pre-charge time.
 */
 
-	b = smbus_read_byte(0x50, SPD_MIN_ROW_PRECHARGE_TIME);
+	b = smbus_read_byte(DIMM0, SPD_MIN_ROW_PRECHARGE_TIME);
 
 	//print_val("\ntRP ",b);
 	if ( b >= (5 * bank)) {
@@ -402,7 +396,7 @@ static void ddr_ram_setup(void)
     Read SPD byte 29, min row pre-charge time.
 */
 
-	b = smbus_read_byte(0x50, SPD_MIN_RAS_TO_CAS_DELAY);
+	b = smbus_read_byte(DIMM0, SPD_MIN_RAS_TO_CAS_DELAY);
 	//print_val("\ntRCD ",b);
 
 	if ( b >= (5 * bank)) c |= 0x0C;		// set tRCD = 5T
@@ -419,7 +413,7 @@ static void ddr_ram_setup(void)
 	/* tRAS is in whole ns */
 	bank = bank >> 2;
 
-	b = smbus_read_byte(0x50, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
+	b = smbus_read_byte(DIMM0, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 	//print_val("\ntRAS ",b);
 	//print_val("\nBank ", bank);
 	if ( b >= (9 * bank)) c |= 0xC0;		// set tRAS = 9T
@@ -438,7 +432,7 @@ static void ddr_ram_setup(void)
 /*
     DRAM Clock  Device 0 Fn 3 Offset 68
 */
-	bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
+	bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 
 	/* Setup DRAM Cycle Time */
 	if ( bank <= 0x50 )
@@ -469,7 +463,7 @@ static void ddr_ram_setup(void)
     Read SPD byte 17, Number of banks on SDRAM device.
 */
 	c = 0x0F;
-	b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM);
+	b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM);
 	if( b == 4) c |= 0x80;
 	else if (b == 2) c |= 0x40;
 
@@ -520,7 +514,7 @@ static void ddr_ram_setup(void)
 
 
 	/* SPD byte 5  # of physical banks */
-	b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1;
+	b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1;
 	c = b | 0x40;
 
 	pci_write_config8(ctrl.d0f3, 0xb0, c);
@@ -532,7 +526,7 @@ static void ddr_ram_setup(void)
 	pci_write_config8(ctrl.d0f3, 0x48, ma);
 	udelay(200);
 
-	c = smbus_read_byte(0x50, SPD_SUPPORTED_BURST_LENGTHS);
+	c = smbus_read_byte(DIMM0, SPD_SUPPORTED_BURST_LENGTHS);
 	c &= 0x08;
 	if ( c == 0x08 )
 	{
@@ -673,7 +667,7 @@ static void ddr_ram_setup(void)
 	pci_write_config8(ctrl.d0f3, 0xED, 0x11);
 
 	/* SPD byte 5  # of physical banks */
-	b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1;
+	b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1;
 
 	/* determine low bond */
 	if( b == 2)
@@ -795,7 +789,7 @@ static void ddr_ram_setup(void)
 */
 	//c = pci_read_config8(ctrl.d0f3, 0x68);
 	//c &= 0x07;
-	//b = smbus_read_byte(0x50, SPD_REFRESH);
+	//b = smbus_read_byte(DIMM0, SPD_REFRESH);
 	//print_val("SPD_REFRESH = ", b);
 
 	pci_write_config8(ctrl.d0f3,0x6a,0x65);
diff --git a/src/northbridge/via/vt8601/raminit.c b/src/northbridge/via/vt8601/raminit.c
index f1ebbe5338..5e7611a3c0 100644
--- a/src/northbridge/via/vt8601/raminit.c
+++ b/src/northbridge/via/vt8601/raminit.c
@@ -34,6 +34,8 @@ it with the version available from LANL.
  */
 /* converted to C 9/2003 Ron Minnich */
 
+#include <spd.h>
+
 /* Set to 1 if your DIMMs are PC133 Note that I'm assuming CPU's FSB
  * frequency is 133MHz. If your CPU runs at another bus speed, you
  * might need to change some of register values.
@@ -178,8 +180,8 @@ static unsigned long spd_module_size(unsigned char slot)
 	/* we may run out of registers ... */
 	unsigned int banks, rows, cols;
 	unsigned int value = 0;
-	/* unsigned int module = ((0x50 + slot) << 1) + 1; */
-	unsigned int module = 0x50 + slot;
+	/* unsigned int module = ((DIMM0 + slot) << 1) + 1; */
+	unsigned int module = DIMM0 + slot;
 
 	/* is the module there? if byte 2 is not 4, then we'll assume it
 	 * is useless.
@@ -220,7 +222,7 @@ static unsigned long spd_module_size(unsigned char slot)
 #if 0
 static int spd_num_chips(unsigned char slot)
 {
-	unsigned int module = 0x50 + slot;
+	unsigned int module = DIMM0 + slot;
 	unsigned int width;
 
 	width = smbus_read_byte(module, 13);
@@ -236,13 +238,13 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 	unsigned char Trp = 1, Tras = 1, casl = 2, val;
 	unsigned char timing = 0xe4;
 	/* read Trp */
-	val = smbus_read_byte(0x50, 27);
+	val = smbus_read_byte(DIMM0, 27);
 	if (val < 2 * T133)
 		Trp = 1;
-	val = smbus_read_byte(0x50, 30);
+	val = smbus_read_byte(DIMM0, 30);
 	if (val < 5 * T133)
 		Tras = 0;
-	val = smbus_read_byte(0x50, 18);
+	val = smbus_read_byte(DIMM0, 18);
 	if (val < 8)
 		casl = 1;
 	if (val < 4)
@@ -366,7 +368,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 			continue;
 
 		/* Read the row densities */
-		size = smbus_read_byte(0x50+slot, 0x1f);
+		size = smbus_read_byte(DIMM0 + slot, 0x1f);
 
 		/* Set the MA map type.
 		 *
diff --git a/src/northbridge/via/vt8623/raminit.c b/src/northbridge/via/vt8623/raminit.c
index 295011b785..b5c78a1337 100644
--- a/src/northbridge/via/vt8623/raminit.c
+++ b/src/northbridge/via/vt8623/raminit.c
@@ -30,6 +30,7 @@
 */
 /* ported and enhanced from assembler level code in coreboot v1 */
 
+#include <spd.h>
 #include <cpu/x86/mtrr.h>
 #include "raminit.h"
 
@@ -101,7 +102,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
     Read SPD byte 17, Number of banks on SDRAM device.
 */
 	c = 0;
-	b = smbus_read_byte(0xa0,17);
+	b = smbus_read_byte(DIMM0,17);
 	print_val("Detecting Memory\nNumber of Banks ",b);
 
 	if( b != 2 ){            // not 16 Mb type
@@ -109,14 +110,14 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 /*
     Read SPD byte 3, Number of row addresses.
 */
-		b = smbus_read_byte(0xa0,3);
+		b = smbus_read_byte(DIMM0,3);
 		print_val("\nNumber of Rows ",b);
 		if( b >= 0x0d ){	// not 64/128Mb (rows <=12)
 
 /*
     Read SPD byte 13, Primary DRAM width.
 */
-			b = smbus_read_byte(0xa0,13);
+			b = smbus_read_byte(DIMM0,13);
 			print_val("\nPriamry DRAM width",b);
 			if( b != 4 )   // mot 64/128Mb (x4)
 				c = 0x80;  // 256Mb
@@ -127,7 +128,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 
     Read SPD byte 4, Number of column addresses.
 */
-		b = smbus_read_byte(0xa0,4);
+		b = smbus_read_byte(DIMM0,4);
 		print_val("\nNo Columns ",b);
 		if( b == 10 || b == 11 ) c |= 0x60;   // 10/11 bit col addr
 		if( b == 9 ) c |= 0x40;           // 9 bit col addr
@@ -149,7 +150,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 
 // Read SPD byte 31 Module bank density
 	c = 0;
-	b = smbus_read_byte(0xa0,31);
+	b = smbus_read_byte(DIMM0,31);
 	if( b & 0x02 ) c = 0x80;         // 2GB
 	else if( b & 0x01) c = 0x40;     // 1GB
 	else if( b & 0x80) c = 0x20;     // 512Mb
@@ -166,7 +167,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 	// set bank zero size
 	pci_write_config8(north,0x5a,c);
 	// SPD byte 5  # of physical banks
-	b = smbus_read_byte(0xa0,5);
+	b = smbus_read_byte(DIMM0,5);
 
 	print_val("\nNo Physical Banks ",b);
 	if( b == 2)
@@ -180,7 +181,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 
 
 	/* Read SPD byte 18 CAS Latency */
-	b = smbus_read_byte(0xa0,18);
+	b = smbus_read_byte(DIMM0,18);
 	print_debug("\nCAS Supported ");
 	if(b & 0x04)
 		print_debug("2 ");
@@ -188,9 +189,9 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 		print_debug("2.5 ");
 	if(b & 0x10)
 		print_debug("3");
-	print_val("\nCycle time at CL X     (nS)",smbus_read_byte(0xa0,9));
-	print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23));
-	print_val("\nCycle time at CL X-1   (nS)",smbus_read_byte(0xa0,25));
+	print_val("\nCycle time at CL X     (nS)",smbus_read_byte(DIMM0,9));
+	print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(DIMM0,23));
+	print_val("\nCycle time at CL X-1   (nS)",smbus_read_byte(DIMM0,25));
 
 
 	if( b & 0x10 ){             // DDR offering optional CAS 3
@@ -198,13 +199,13 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 		c = 0x30;
 		/* see if we can better it */
 		if( b & 0x08 ){     // DDR mandatory CAS 2.5
-			if( smbus_read_byte(0xa0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5
+			if( smbus_read_byte(DIMM0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5
 				print_debug("\nWe can do CAS 2.5");
 				c = 0x20;
 			}
 		}
 		if( b & 0x04 ){     // DDR mandatory CAS 2
-			if( smbus_read_byte(0xa0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2
+			if( smbus_read_byte(DIMM0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2
 				print_debug("\nWe can do CAS 2");
 				c = 0x10;
 			}
@@ -213,7 +214,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 		print_debug("\nStarting at CAS 2.5");
 		c = 0x20;          // assume CAS 2.5
 		if( b & 0x04){      // Should always happen
-			if( smbus_read_byte(0xa0,23) <= 0x75){ // we can manage 133Mhz at CAS 2
+			if( smbus_read_byte(DIMM0,23) <= 0x75){ // we can manage 133Mhz at CAS 2
 				print_debug("\nWe can do CAS 2");
 				c = 0x10;
 			}
@@ -253,7 +254,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
     Read SPD byte 27, min row pre-charge time.
 */
 
-	b = smbus_read_byte(0xa0,27);
+	b = smbus_read_byte(DIMM0,27);
 	print_val("\ntRP ",b);
 	if( b > 0x3c )           // set tRP = 3T
 		c |= 0x80;
@@ -265,7 +266,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
     Read SPD byte 29, min row pre-charge time.
 */
 
-	b = smbus_read_byte(0xa0,29);
+	b = smbus_read_byte(DIMM0,29);
 	print_val("\ntRCD ",b);
 	if( b > 0x3c )           // set tRCD = 3T
 		c |= 0x04;
@@ -277,7 +278,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
     Read SPD byte 30, device min active to pre-charge time.
 */
 
-	b = smbus_read_byte(0xa0,30);
+	b = smbus_read_byte(DIMM0,30);
 	print_val("\ntRAS ",b);
 	if( b > 0x25 )           // set tRAS = 6T
 		c |= 0x40;
@@ -288,7 +289,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 
     Read SPD byte 17, Number of banks on SDRAM device.
 */
-	b = smbus_read_byte(0xa0,17);
+	b = smbus_read_byte(DIMM0,17);
 	if( b == 4) c |= 0x02;
 	else if (b == 2) c |= 0x01;
 
@@ -342,7 +343,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 	pci_write_config8(north,0x6d,0x044);
 	pci_write_config8(north,0x67,0x3a);
 
-	b = smbus_read_byte(0xa0,5); // SPD byte 5  # of physical banks
+	b = smbus_read_byte(DIMM0,5); // SPD byte 5  # of physical banks
 	if( b > 1) {
                 // Increase drive control when there is more than 1 physical bank
 		pci_write_config8(north,0x6c,0x84);   // Drive control: MA, DQS, MD/CKE
diff --git a/src/northbridge/via/vx800/detection.c b/src/northbridge/via/vx800/detection.c
index 6bbfef0168..ce0ee39e18 100644
--- a/src/northbridge/via/vx800/detection.c
+++ b/src/northbridge/via/vx800/detection.c
@@ -19,14 +19,9 @@
 
 /* FIXME this should go away */
 static const struct mem_controller ctrl = {
-	.channel0 = {0x50, 0x51},
+	.channel0 = {DIMM0, DIMM1},
 };
 
-#define SMBUS_ADDR_CH_A_1       0xA0	/* Dimmx */
-#define SMBUS_ADDR_CH_A_2       0xA2	/* Dimmx */
-#define SMBUS_ADDR_CH_B_1       0xA4	/* Dimmx */
-#define SMBUS_ADDR_CH_B_2       0xA6	/* Dimmx */
-
 /* read data */
 CB_STATUS GetSPDData(u8 Slot, u8 Length, u8 *Buf);
 void DRAMCmdRate(DRAM_SYS_ATTR *DramAttr);