diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-05 21:02:23 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-09 21:36:47 +0200 |
| commit | e7aeb2f60212077521f7d71a4f485c8f4a26f6c6 (patch) | |
| tree | 2c9b89bd9d2bd173aaee4f7e36e65217573d1fc7 /src/northbridge/via/vx900 | |
| parent | 83b9703505becf34728a2286a3ad3e6749a4d619 (diff) | |
src/northbridge/via: Remove commented code
Change-Id: Ic589b26c6c94df12e1fe218d079018db8b38fbd9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16898
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/via/vx900')
| -rw-r--r-- | src/northbridge/via/vx900/chrome9hd.c | 1 | ||||
| -rw-r--r-- | src/northbridge/via/vx900/lpc.c | 2 | ||||
| -rw-r--r-- | src/northbridge/via/vx900/raminit_ddr3.c | 10 |
3 files changed, 2 insertions, 11 deletions
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index 03c8e0cf55..c99f10e889 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -306,7 +306,6 @@ static void chrome9hd_init(device_t dev) vga_misc_mask(1 << 0, 1 << 0); /* FIXME: recheck; Enable Base VGA 16 Bits Decode */ - ////pci_mod_config8(host, 0x4e, 0, 1<<4); u32 fb_address = pci_read_config32(dev, PCI_BASE_ADDRESS_2); fb_address &= ~0x0F; diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index 4f3d704a8c..a9d24df91f 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -77,7 +77,7 @@ static void vx900_lpc_dma_setup(device_t dev) /* Enable Positive South Module PCI Cycle Decoding */ /* FIXME: Setting this seems to hang our system */ - //pci_mod_config8(dev, 0x58, 0, 1<<4); + /* Positive decoding for ROM + APIC + On-board IO ports */ pci_mod_config8(dev, 0x6c, 0, (1 << 2) | (1 << 3) | (1 << 7)); /* Enable DMA channels. BIOS guide recommends DMA channel 2 off */ diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index aff62f2773..4878571742 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -326,9 +326,8 @@ static void vx900_dram_write_init_config(void) /* Fast cycle control for CPU-to-DRAM Read Cycle 0:Disabled. * This CPU bus controller will wait for all data */ - ////pci_mod_config8(HOST_BUS, 0x51, (1 << 7), 0); + /* Memory to CPU bus Controller Conversion Mode 1: Synchronous mode */ - ////pci_mod_config8(HOST_BUS, 0x54, 0, (1 << 1)); } static void dram_find_spds_ddr3(const dimm_layout * addr, dimm_info * dimm) @@ -1335,7 +1334,6 @@ static void vx900_dram_calibrate_transmit_delays(delay_range * tx_dq, /* FIXME: Except that we have not yet told the MCU what * the geometry of the DIMM is, hence we don't trust * this test for now */ - ////continue; } /* Good. We should be able to use this DIMM */ /* That's it. We're done */ @@ -1614,14 +1612,8 @@ static void vx900_dram_write_final_config(ramctr_timing * ctrl) /* Tri-state MCSi# when rank is in self-refresh */ pci_mod_config8(MCU, 0x99, 0, 0x0f); - ////pci_write_config8(MCU, 0x69, 0xe7); /* Enable paging mode and 8 page registers */ pci_mod_config8(MCU, 0x69, 0, 0xe5); - ////pci_write_config8(MCU, 0x72, 0x0f); - - ////pci_write_config8(MCU, 0x97, 0xa4); /* self-refresh */ - ////pci_write_config8(MCU, 0x98, 0xba); /* self-refresh II */ - ////pci_write_config8(MCU, 0x9a, 0x80); /* self-refresh III */ /* Enable automatic triggering of short ZQ calibration */ pci_write_config8(MCU, 0xc8, 0x80); |