diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-10-18 11:02:56 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-19 17:20:44 +0200 |
| commit | 5cf88249236220ba4e1dc991e99b6bd823cf8de8 (patch) | |
| tree | b762a5d09d49fc2c4b34d14b3476dde32f769f70 /src/northbridge/via/vx900/chrome9hd.c | |
| parent | f7bfc34942f5dda173c30f82323e13afb2045a21 (diff) | |
via/vx900: Remove GFXUMA and use of related global variables
Remove global variables uma_memory_base and uma_memory_size
from builds with via/vx900 northbridge, as these variables can be kept
within the chipset.
Change-Id: I9f8aea4836d81e704eae6a0f2cefc7fd4586b8b8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5721
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/northbridge/via/vx900/chrome9hd.c')
| -rw-r--r-- | src/northbridge/via/vx900/chrome9hd.c | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index 55e2a9679f..bf0b278a76 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -220,12 +220,6 @@ static void chrome9hd_handle_uma(device_t dev) /* Mirror mirror, shiny glass, tell me that is not my ass */ u32 fb_size = chrome9hd_fb_size() >> 20; - //uma_resource(dev, 0x18, uma_memory_base>>10, uma_memory_size>>10); - - printk(BIOS_DEBUG, "UMA base 0x%.8llx (%lluMB)\n", uma_memory_base, - uma_memory_base >> 20); - printk(BIOS_DEBUG, "UMA size 0x%.8llx (%lluMB)\n", uma_memory_size, - uma_memory_size >> 20); u8 fb_pow = 0; while (fb_size >> fb_pow) fb_pow++; @@ -286,13 +280,13 @@ static void chrome9hd_biosguide_init_seq(device_t dev) chrome9hd_handle_uma(dev); - /* Step 8 - Enable memory base register on the GFX */ - if (uma_memory_base == 0) + uint64_t gfx_base = get_uma_memory_base(); + if (gfx_base == 0) die("uma_memory_base not set. Abandon ship!\n"); - printk(BIOS_DEBUG, "UMA base 0x%.10llx (%lluMB)\n", uma_memory_base, - uma_memory_base >> 20); - vga_sr_write(0x6d, (uma_memory_base >> 21) & 0xff); /* base 28:21 */ - vga_sr_write(0x6e, (uma_memory_base >> 29) & 0xff); /* base 36:29 */ + + /* Step 8 - Enable memory base register on the GFX */ + vga_sr_write(0x6d, (gfx_base >> 21) & 0xff); /* base 28:21 */ + vga_sr_write(0x6e, (gfx_base >> 29) & 0xff); /* base 36:29 */ vga_sr_write(0x6f, 0x00); /* base 43:37 */ /* Step 9 - Set SID/VID */ |