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authorAlexandru Gagniuc <mr.nuke.me@gmail.com>2013-06-09 16:06:07 -0500
committerRonald G. Minnich <rminnich@gmail.com>2013-06-10 22:58:21 +0200
commit23211b0200eac11c64fe9dadadb5ec5ef1deabc6 (patch)
tree865130c93105ab780e90d252a9fb66a0ad599380 /src/northbridge/via/vx900/Makefile.inc
parent7d31e7c13897e4b2548136c7a6f701b9121b7ad3 (diff)
VIA VX900: Add minimal ramstage needed to boot linux
This is the minimal code needed to get past ramstage, load SeaBIOS, jump to GRUB2, and boot linux (or load memtest). See individual source files for the status of each individual component. Change-Id: Ib7d5d7593c945f18af2c2fc5e0ae689ba66131a2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3419 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/via/vx900/Makefile.inc')
-rw-r--r--src/northbridge/via/vx900/Makefile.inc12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index 1586c87751..13d7de65ed 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -31,6 +31,18 @@ romstage-y += ./../../../southbridge/via/common/early_smbus_wait_until_ready.c
romstage-y += ./../../../drivers/pc80/udelay_io.c
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += ./../../../lib/cbmem.c
+ramstage-y += pci_util.c
+ramstage-y += pcie.c
+ramstage-y += northbridge.c
+ramstage-y += chrome9hd.c
+ramstage-y += traf_ctrl.c
+ramstage-y += sata.c
+ramstage-y += lpc.c
+
+# The buildsystem only includes this file if CONFIG_VGA is selected.
+# We need to do some VGA I/O before the VGA can be initialized. We can make good
+# use of some of the functions there, so include them unconditionally
+ramstage-y += ./../../../drivers/pc80/vga/vga_io.c
chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc