Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

16 files changed, 137 insertions, 137 deletions

diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c
index c3097cf2cb..172a8de148 100644
--- a/src/northbridge/via/vx800/dev_init.c
+++ b/src/northbridge/via/vx800/dev_init.c
@@ -30,8 +30,8 @@ CB_STATUS VerifyChc(void);
 
 /*===================================================================
 Function   : DRAMRegInitValue()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
@@ -68,7 +68,7 @@ static const u8 DramRegTbl[][3] = {
 	// {0x79, 0x00, 0x8F },
 	{0x85, 0x00, 0x00},
 	// {0x90, 0x87, 0x78 },
-	// {0x91, 0x00, 0x46 }, 
+	// {0x91, 0x00, 0x46 },
 	{0x40, 0x00, 0x00},
 
 	{0, 0, 0}
@@ -155,8 +155,8 @@ void DRAMRegInitValue(DRAM_SYS_ATTR *DramAttr)
 
 /*===================================================================
 Function   : DRAMInitializeProc()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
@@ -176,7 +176,7 @@ static BOOLEAN ChkForExistLowBank(void)
 	Address = (u32 *) 4;
 	*Address = EXIST_TEST_PATTERN;
 
-	// _asm {WBINVD}   
+	// _asm {WBINVD}
 	WaitMicroSec(100);
 	Address = (u32 *) 8;
 	data32 = *Address;
@@ -223,7 +223,7 @@ void DRAMInitializeProc(DRAM_SYS_ATTR *DramAttr)
 			SetEndingAddr(DramAttr, idx, 0x10); /* Assume 1G size */
 			if (idx < 4) /* CHA init */
 				InitDDR2CHA(DramAttr);	// temp wjb 2007/1 only for compiling
-			// in the function InitDDR2,the parameter is no need   
+			// in the function InitDDR2,the parameter is no need
 			Status = ChkForExistLowBank();
 			if (Status == TRUE) {
 				PRINT_DEBUG_MEM(" S\r");
@@ -247,8 +247,8 @@ void DRAMInitializeProc(DRAM_SYS_ATTR *DramAttr)
 
 /*===================================================================
 Function   : DRAMSetVRNUM()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 		  PhyRank:   Physical Rank number
@@ -285,14 +285,14 @@ void DRAMSetVRNum(DRAM_SYS_ATTR *DramAttr, u8 PhyRank /* physical rank */,
 
 /*===================================================================
 Function   : SetEndingAddr()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 		  VirRank:    Virtual Rank number
-		  Value:       (value) add or subtract value to this and after banks 
+		  Value:       (value) add or subtract value to this and after banks
 Output     : Void
-Purpose   : Set ending address of virtual rank specified by VirRank 
+Purpose   : Set ending address of virtual rank specified by VirRank
 ===================================================================*/
 
 void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank /* ending address
@@ -312,8 +312,8 @@ void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank /* ending address
 
 /*===================================================================
 Function   : InitDDR2()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
@@ -522,13 +522,13 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr)
 
 /*===================================================================
 Function   : InitDDR2_CHB()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
 Purpose   : Initialize DDR2 of CHB by standard sequence
-Reference  : 
+Reference  :
 ===================================================================*/
 /*//		                 DLL:	      Enable				  Reset
 static const  u32 CHB_MRS_DLL_150[2] =	{ 0x00020200 | (1 << 20), 0x00000800 };	// with 150 ohm (A17=1, A9=1), (A11=1)(cpu address)
@@ -569,7 +569,7 @@ void InitDDR2CHB(
 
     Data = 0x80;
     pci_write_config8(MEMCTRL, 0x54, Data);
-	
+
     // step3.
     //disable bank paging and multi page
     Data=pci_read_config8(MEMCTRL, 0x69);
@@ -579,18 +579,18 @@ void InitDDR2CHB(
     Data=pci_read_config8(MEMCTRL, 0xd3);
     Data |= 0x80;
     pci_write_config8(MEMCTRL, 0xd3, Data);
-	
+
     //step 4. Initialize CHB begin
     Data=pci_read_config8(MEMCTRL, 0xd3);
     Data |= 0x40;
     pci_write_config8(MEMCTRL, 0xd3, Data);
-	
+
     //Step 5. NOP command enable
     Data=pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
     Data  |= 0x08;
     pci_write_config8(MEMCTRL, 0xd7, Data);
-   
+
     //Step 6.  issue a nop cycle,RegD3[7]  0 -> 1
     Data=pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0x7F;
@@ -604,7 +604,7 @@ void InitDDR2CHB(
     // Loop 200us
     for (Idx = 0; Idx < 0x10; Idx++)
         WaitMicroSec(10);
-	
+
     // Step 8.
     // all banks precharge command enable
     Data=pci_read_config8(MEMCTRL, 0xd7);
@@ -618,7 +618,7 @@ void InitDDR2CHB(
     pci_write_config8(MEMCTRL, 0xd3, Data);
     Data |=  0x80;
     pci_write_config8(MEMCTRL, 0xd3, Data);
-	
+
    //step10. EMRS enable
     Data=pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
@@ -661,7 +661,7 @@ void InitDDR2CHB(
     Data |= 0x00;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
-    //step 14. MSR DLL Reset 
+    //step 14. MSR DLL Reset
     AccessAddr = CHB_MRS_DLL_150[1] >> 3;
     Data =(u8) (AccessAddr & 0xff);
     pci_write_config8(MEMCTRL, 0xd9, Data);
@@ -691,7 +691,7 @@ void InitDDR2CHB(
     Data |= 0x10;
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
-   
+
    // step17. issue precharge all cycle
     Data=pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0x7F;
@@ -718,7 +718,7 @@ void InitDDR2CHB(
 
     WaitMicroSec(200);
     }
-	
+
     //step22. MSR enable
     Data=pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
@@ -730,7 +730,7 @@ void InitDDR2CHB(
     Data |= 0x00;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
-  
+
     //the SDRAM parameters.(Burst Length, CAS# Latency , Write recovery etc.)
     //-------------------------------------------------------------
     //Burst Length : really offset Rx6c[1]
@@ -773,7 +773,7 @@ void InitDDR2CHB(
     pci_write_config8(MEMCTRL, 0xd3, Data);
     Data |=  0x80;
     pci_write_config8(MEMCTRL, 0xd3, Data);
-	
+
     //step 25. EMRS enable
     Data=pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
@@ -784,7 +784,7 @@ void InitDDR2CHB(
     Data &= 0xC7;
     Data |= 0x08;
     pci_write_config8(MEMCTRL, 0xd3, Data);
-	
+
 
     //step 26. OCD default
      AccessAddr = (CHB_OCD_Default_150ohm) >> 3;
@@ -805,7 +805,7 @@ void InitDDR2CHB(
     pci_write_config8(MEMCTRL, 0xd3, Data);
     Data |=  0x80;
     pci_write_config8(MEMCTRL, 0xd3, Data);
-	
+
      //step 25. EMRS enable
     Data=pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
@@ -859,12 +859,12 @@ void InitDDR2CHB(
     Data |= 0x00;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
-    //step 31.  exit the initialization mode 
+    //step 31.  exit the initialization mode
     Data=pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0xBF;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
-	
+
     //step 32. Enable bank paging and multi page
     Data=pci_read_config8(MEMCTRL, 0x69);
     Data |= 0x03;
@@ -874,13 +874,13 @@ void InitDDR2CHB(
 
 /*===================================================================
 Function   : InitDDR2CHC()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
 Purpose   : Initialize DDR2 of CHC by standard sequence
-Reference  : 
+Reference  :
 ===================================================================*/
 //                      DDR2                 CL=2          CL=3 CL=4   CL=5     (Burst type=interleave)(WR fine tune in code)
 static const u16 CHC_MRS_table[4] = { 0x22B, 0x23B, 0x24B, 0x25B };	// Use 1X-bandwidth MA table to init DRAM
@@ -1102,7 +1102,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr)
 	Status = VerifyChc();
 	if (Status != CB_SUCCESS)
 		PRINT_DEBUG_MEM("Error!!!!CHC init error!\r");
-	//step 31.  exit the initialization mode 
+	//step 31.  exit the initialization mode
 	Data = pci_read_config8(MEMCTRL, 0xdb);
 	Data &= 0x9F;
 	pci_write_config8(MEMCTRL, 0xdb, Data);
diff --git a/src/northbridge/via/vx800/dqs_search.c b/src/northbridge/via/vx800/dqs_search.c
index 785d775baf..c4971d1b17 100644
--- a/src/northbridge/via/vx800/dqs_search.c
+++ b/src/northbridge/via/vx800/dqs_search.c
@@ -22,8 +22,8 @@ void SetDQSOutputCHB(DRAM_SYS_ATTR * DramAttr);
 
 /*===================================================================
 Function   : DRAMDQSOutputSearchCHA()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
@@ -40,12 +40,12 @@ void DRAMDQSOutputSearch(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : SetDQSOutputCHA()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
-Purpose   :  according the frequence set CHA DQS output 
+Purpose   :  according the frequence set CHA DQS output
 ===================================================================*/
 void SetDQSOutputCHA(DRAM_SYS_ATTR * DramAttr)
 {
@@ -80,8 +80,8 @@ void SetDQSOutputCHA(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : DRAMDQSInputSearch()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
diff --git a/src/northbridge/via/vx800/dram_util.c b/src/northbridge/via/vx800/dram_util.c
index 342a6e0454..7688ab34a8 100644
--- a/src/northbridge/via/vx800/dram_util.c
+++ b/src/northbridge/via/vx800/dram_util.c
@@ -30,11 +30,11 @@ void WaitMicroSec(UINTN MicroSeconds)
 
 /*===================================================================
 Function   : via_write_phys()
-Precondition : 
+Precondition :
 Input      :  addr
                   value
 Output     : void
-Purpose    : 
+Purpose    :
 Reference  : None
 ===================================================================*/
 
@@ -47,10 +47,10 @@ void via_write_phys(volatile u32 addr, volatile u32 value)
 
 /*===================================================================
 Function   : via_read_phys()
-Precondition : 
+Precondition :
 Input      :  addr
-Output     : u32 
-Purpose    : 
+Output     : u32
+Purpose    :
 Reference  : None
 ===================================================================*/
 
@@ -63,10 +63,10 @@ u32 via_read_phys(volatile u32 addr)
 
 /*===================================================================
 Function   : DimmRead()
-Precondition : 
+Precondition :
 Input      :  x
-Output     : u32 
-Purpose    : 
+Output     : u32
+Purpose    :
 Reference  : None
 ===================================================================*/
 
@@ -80,13 +80,13 @@ u32 DimmRead(volatile u32 x)
 
 /*===================================================================
 Function   : DramBaseTest()
-Precondition : this function used to verify memory  
-Input      :  
+Precondition : this function used to verify memory
+Input      :
                  BaseAdd,
                  length,
                  mode
 Output     : u32
-Purpose    :write into and read out to verify if dram is correct 
+Purpose    :write into and read out to verify if dram is correct
 Reference  : None
 ===================================================================*/
 BOOLEAN DramBaseTest(u32 BaseAdd, u32 Length,
@@ -170,8 +170,8 @@ BOOLEAN DramBaseTest(u32 BaseAdd, u32 Length,
 
 /*===================================================================
 Function   : DumpRegisters()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
                 pPCIPPI,
                 DevNum,
                 FuncNum
@@ -209,8 +209,8 @@ void DumpRegisters(INTN DevNum, INTN FuncNum)
 
 /*===================================================================
 Function   : dumpnorth()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
                 pPCIPPI,
                 Func
 Output     : Void
diff --git a/src/northbridge/via/vx800/driving_setting.c b/src/northbridge/via/vx800/driving_setting.c
index c6a7edda05..bdba494d85 100644
--- a/src/northbridge/via/vx800/driving_setting.c
+++ b/src/northbridge/via/vx800/driving_setting.c
@@ -58,7 +58,7 @@ void DRAMDriving(DRAM_SYS_ATTR * DramAttr)
 /*
 ODT	Control	for DQ/DQS/CKE/SCMD/DCLKO in ChA & ChB
 which include driving enable/range and strong/weak selection
- 
+
 Processing: According to DRAM frequency to ODT control bits.
       		Because function enable bit must be the last one to be set.
       		So the register VIA_NB3DRAM_REGD4 and VIA_NB3DRAM_REGD3 should be
@@ -125,7 +125,7 @@ static const u8 ODTLookup_TBL[ODTLookup_Tbl_count][3] = {
 };
 
 #define ODT_Table_Width_DDR2		4
-//                                                                                               RxD6   RxD3 
+//                                                                                               RxD6   RxD3
 static const u8 ODT_Control_DDR2[ODT_Table_Width_DDR2] = { 0xFC, 0x01 };
 
 void DrivingODT(DRAM_SYS_ATTR * DramAttr)
diff --git a/src/northbridge/via/vx800/examples/driving_clk_phase_data.c b/src/northbridge/via/vx800/examples/driving_clk_phase_data.c
index a93c9a03c4..5e8e214d1f 100644
--- a/src/northbridge/via/vx800/examples/driving_clk_phase_data.c
+++ b/src/northbridge/via/vx800/examples/driving_clk_phase_data.c
@@ -20,7 +20,7 @@
 
  #include "northbridge/via/vx800/driving_clk_phase_data.h"
 
-// DQS	Driving  
+// DQS	Driving
 //Reg0xE0, 0xE1
 // According to #Bank to set DRAM DQS Driving
 //	                          #Bank	   1	 2     3     4	   5	 6     7     8
@@ -161,7 +161,7 @@ static const  u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM
         {0x8C,  0xFC,  0x03,  0x03,  0x03,  0x03 }
     };
 
-/*static const  u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = 
+/*static const  u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] =
     {
         //    (And NOT) DDR800 DDR667 DDR533 DDR400
         //Reg  Mask  Value Value Value Value
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index 8db60237b7..63755c3181 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -362,7 +362,7 @@ g)      Rx73h = 32h
 	/* decide if this is a s3 wakeup or a normal boot */
 	boot_mode = acpi_is_wakeup_early_via_vx800();
 	/*add this, to transfer "cpu restart" to "cold boot"
-	   When this boot is not a S3 resume, and PCI registers had been written, 
+	   When this boot is not a S3 resume, and PCI registers had been written,
 	   then this must be a cpu restart(result of os reboot cmd). so we need a real "cold boot". */
 	if ((boot_mode != 3)
 	    && (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) {
@@ -371,7 +371,7 @@ g)      Rx73h = 32h
 
 	/*x86 cold boot I/O cmd */
 	enable_smbus();
-	//smbus_fixup(&ctrl);// this fix does help vx800!, but vx855 no need this 
+	//smbus_fixup(&ctrl);// this fix does help vx800!, but vx855 no need this
 
 	if (bist == 0) {
 		// CAR need mtrr untill mem is ok, so i disable this early_mtrr_init();
@@ -441,7 +441,7 @@ g)      Rx73h = 32h
 
 	/*
 	   For coreboot most time of S3 resume is the same as normal boot, so some memory area under 1M become dirty,
-	   so before this happen, I need to backup the content of mem to top-mem. 
+	   so before this happen, I need to backup the content of mem to top-mem.
 	   I will reserve the 1M top-men in LBIO table in coreboot_table.c and recovery the content of 1M-mem in wakeup.c
 	 */
 #if PAYLOAD_IS_SEABIOS==1	//
@@ -449,7 +449,7 @@ g)      Rx73h = 32h
 		/*   some idea of Libo.Feng at amd.com in  http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html
 		   I want move the 1M data, I have to set some MTRRs myself. */
 		/* seting mtrr before back memoy save s3 resume time about 0.14 seconds */
-		/*because CAR stack use cache, and here to use cache , must be careful, 
+		/*because CAR stack use cache, and here to use cache , must be careful,
 		   1 during these mtrr code, must no function call, (after this mtrr, I think it should be ok to use function)
 		   2 before stack switch, no use variable that have value set before this
 		   3 due to 2, take care of "cpu_reset", I directlly set it to ZERO.
@@ -462,7 +462,7 @@ g)      Rx73h = 32h
 		u32 memtop4 =
 		    *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000 +
 		    0xe0000;
-		/*      __asm__ volatile (              
+		/*      __asm__ volatile (
 		   "movl    $0x204, %%ecx\n\t"
 		   "xorl    %%edx, %%edx\n\t"
 		   "movl     %0,%%eax\n\t"
@@ -478,7 +478,7 @@ g)      Rx73h = 32h
 		   "wrmsr\n\t"
 		   ::"g"(memtop2)
 		   );
-		   __asm__ volatile (           
+		   __asm__ volatile (
 		   "movl    $0x206, %%ecx\n\t"
 		   "xorl    %%edx, %%edx\n\t"
 		   "movl     %0,%%eax\n\t"
@@ -494,7 +494,7 @@ g)      Rx73h = 32h
 		   "wrmsr\n\t"
 		   ::"g"(memtop1)
 		   );
-		   __asm__ volatile (       
+		   __asm__ volatile (
 		   "movl    $0x208, %ecx\n\t"
 		   "xorl    %edx, %edx\n\t"
 		   "movl    $0,%eax\n\t"
@@ -512,21 +512,21 @@ g)      Rx73h = 32h
 		 */
 		// WAKE_MEM_INFO is  inited in get_set_top_available_mem in tables.c
 		// these two memcpy not not be enabled if set the MTRR around this two lines.
-		/*__asm__ volatile (		
+		/*__asm__ volatile (
 	 			"movl    $0, %%esi\n\t"
         "movl    %0, %%edi\n\t"
        	"movl    $0xa0000, %%ecx\n\t"
        	"shrl    $2, %%ecx\n\t"
-        "rep movsd\n\t"    
-        ::"g"(memtop3)        
+        "rep movsd\n\t"
+        ::"g"(memtop3)
    	);
-	__asm__ volatile (		
+	__asm__ volatile (
 	 			"movl    $0xe0000, %%esi\n\t"
         "movl    %0, %%edi\n\t"
        	"movl    $0x20000, %%ecx\n\t"
        	"shrl    $2, %%ecx\n\t"
-        "rep movsd\n\t"    
-        ::"g"(memtop4)        
+        "rep movsd\n\t"
+        ::"g"(memtop4)
    	);*/
 		print_debug("copy memory to high memory to protect s3 wakeup vector code \n");	//this can have function call, because no variable used before this
 		memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) -
@@ -537,22 +537,22 @@ g)      Rx73h = 32h
 		       (unsigned char *) 0xe0000, 0x20000);
 
 		/* restore the MTRR previously modified. */
-/*		__asm__ volatile (	
-        "wbinvd\n\t"     			
+/*		__asm__ volatile (
+        "wbinvd\n\t"
         "xorl    %edx, %edx\n\t"
        	"xorl    %eax, %eax\n\t"
        	"movl    $0x204, %ecx\n\t"
         "wrmsr\n\t"
-	 			"movl    $0x205, %ecx\n\t"                                      
-        "wrmsr\n\t"        
+	 			"movl    $0x205, %ecx\n\t"
+        "wrmsr\n\t"
 	 			"movl    $0x206, %ecx\n\t"
         "wrmsr\n\t"
-	 			"movl    $0x207, %ecx\n\t"                     
-        "wrmsr\n\t"        
-	 			"movl    $0x208, %ecx\n\t"                     
-        "wrmsr\n\t"        
-	 			"movl    $0x209, %ecx\n\t"                     
-        "wrmsr\n\t"        
+	 			"movl    $0x207, %ecx\n\t"
+        "wrmsr\n\t"
+	 			"movl    $0x208, %ecx\n\t"
+        "wrmsr\n\t"
+	 			"movl    $0x209, %ecx\n\t"
+        "wrmsr\n\t"
 		);*/
 	}
 #endif
diff --git a/src/northbridge/via/vx800/final_setting.c b/src/northbridge/via/vx800/final_setting.c
index 97cc21820a..9ec31b58da 100644
--- a/src/northbridge/via/vx800/final_setting.c
+++ b/src/northbridge/via/vx800/final_setting.c
@@ -64,8 +64,8 @@ void DRAMRefreshCounter(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : DRAMRegFinalValue()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		   DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
 		                    in MotherBoard
 Output     : Void
diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c
index 47a99c3cc1..03daeec342 100644
--- a/src/northbridge/via/vx800/freq_setting.c
+++ b/src/northbridge/via/vx800/freq_setting.c
@@ -230,7 +230,7 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr)
 		DramAttr->DramFreq = DIMMFREQ_200;
 		DramAttr->DramCyc = 1000;
 	}
-	//if set the frequence mannul                
+	//if set the frequence mannul
 	PRINT_DEBUG_MEM("Dram Frequency:");
 	PRINT_DEBUG_MEM_HEX16(DramAttr->DramFreq);
 	PRINT_DEBUG_MEM(" \r");
diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c
index 4dfe843bae..37e559c026 100644
--- a/src/northbridge/via/vx800/northbridge.c
+++ b/src/northbridge/via/vx800/northbridge.c
@@ -118,7 +118,7 @@ static u32 find_pci_tolm(struct bus *bus)
 
 static void pci_domain_set_resources(device_t dev)
 {
-	/* 
+	/*
 	 * the order is important to find the correct ram size.
 	 */
 	u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
diff --git a/src/northbridge/via/vx800/rank_map.c b/src/northbridge/via/vx800/rank_map.c
index 6c88c68953..3eada63329 100644
--- a/src/northbridge/via/vx800/rank_map.c
+++ b/src/northbridge/via/vx800/rank_map.c
@@ -32,8 +32,8 @@ void DRAMPRToVRMapping(DRAM_SYS_ATTR * DramAttr);
 
 /*===================================================================
 Function   : DRAMBankInterleave()
-Precondition : 
-Input        : 
+Precondition :
+Input        :
 		   DramAttr: pointer point to  DRAMSYSATTR  which consist the DDR and Dimm information in MotherBoard
 Output     :  Void
 Purpose   :  STEP 13 Set Bank Interleave  VIANB3DRAMREG69[7:6] 00:No Interleave 01:2 Bank 10:4 Bank	11:8 Bank
@@ -85,11 +85,11 @@ void DRAMBankInterleave(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : DRAMSizingMATypeM()
-Precondition : 
+Precondition :
 Input        :
 		   DramAttr: pointer point to  DRAMSYSATTR  which consist the DDR and Dimm information in MotherBoard
 Output     :  Void
- Purpose  : STEP 14  1 DRAM Sizing 2  Fill MA type 3 Prank to vrankMapping 
+ Purpose  : STEP 14  1 DRAM Sizing 2  Fill MA type 3 Prank to vrankMapping
 ===================================================================*/
 void DRAMSizingMATypeM(DRAM_SYS_ATTR * DramAttr)
 {
@@ -103,8 +103,8 @@ void DRAMSizingMATypeM(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : DRAMClearEndingAddress()
-Precondition : 
-Input        : 
+Precondition :
+Input        :
 		   DramAttr: pointer point to  DRAMSYSATTR  which consist the DDR and Dimm information in MotherBoard
 Output     : Void
 Purpose   : clear Ending and Start adress from 0x40-4f to zero
@@ -120,8 +120,8 @@ void DRAMClearEndingAddress(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : DRAMSizingEachRank()
-Precondition : 
-Input        : 
+Precondition :
+Input        :
 		   DramAttr: pointer point to  DRAMSYSATTR  which consist the DDR and Dimm information in MotherBoard
 Output     : Void
 Purpose   : Sizing each Rank invidually, by number of rows column banks pins, be care about 128bit
@@ -189,8 +189,8 @@ void DRAMSizingEachRank(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : DRAMSetRankMAType()
-Precondition : 
-Input       : 
+Precondition :
+Input       :
 		  DramAttr: pointer point to  DRAMSYSATTR  which consist the DDR and Dimm information in MotherBoard
 Output     : Void
 Purpose   : set the matype Reg by MAMapTypeTbl, which the rule can be found in memoryinit
@@ -258,11 +258,11 @@ void DRAMSetRankMAType(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : DRAMSetEndingAddress()
-Precondition : 
-Input      :  
+Precondition :
+Input      :
 		  DramAttr: pointer point to  DRAMSYSATTR  which consist the DDR and Dimm information in MotherBoard
 Output     : Void
-Purpose   : realize the Vrank 40...Reg (Start and Ending Regs). Vrank have  same order with phy Rank, Size is actual Size  
+Purpose   : realize the Vrank 40...Reg (Start and Ending Regs). Vrank have  same order with phy Rank, Size is actual Size
 ===================================================================*/
 void DRAMSetEndingAddress(DRAM_SYS_ATTR * DramAttr)
 {
@@ -311,8 +311,8 @@ void DRAMSetEndingAddress(DRAM_SYS_ATTR * DramAttr)
 
 /*===================================================================
 Function   : DRAMPRToVRMapping()
-Precondition : 
-Input       : 
+Precondition :
+Input       :
 		  DramAttr: pointer point to  DRAMSYSATTR  which consist the DDR and Dimm information in MotherBoard
 Output     : Void
 Purpose   : set the Vrank-prank map with the same order
diff --git a/src/northbridge/via/vx800/timing_setting.c b/src/northbridge/via/vx800/timing_setting.c
index a1d8e74812..7668b22e0b 100644
--- a/src/northbridge/via/vx800/timing_setting.c
+++ b/src/northbridge/via/vx800/timing_setting.c
@@ -72,7 +72,7 @@ void DRAMTimingSetting(DRAM_SYS_ATTR * DramAttr)
 
 /*
 Set DRAM Timing: CAS Latency for DDR1
-D0F3RX62 bit[0:2] for CAS Latency; 
+D0F3RX62 bit[0:2] for CAS Latency;
 */
 void SetCL(DRAM_SYS_ATTR * DramAttr)
 {
diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c
index 72420981ff..6fe8194922 100644
--- a/src/northbridge/via/vx800/uma_ram_setting.c
+++ b/src/northbridge/via/vx800/uma_ram_setting.c
@@ -139,7 +139,7 @@ void SetUMARam(void)
 
 //      vga_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VGA, 0);
 
-	//RxB2 may be for S.L. and RxB1 may be for L. L. 
+	//RxB2 may be for S.L. and RxB1 may be for L. L.
 	// It is different from Spec.
 	ByteVal = SLD1F0Val;
 	pci_write_config8(vga_dev, 0xb2, ByteVal);
@@ -256,7 +256,7 @@ void SetUMARam(void)
 	}
 	outb(ByteVal, 0x03d5);
 
-	// Set frame buffer size 
+	// Set frame buffer size
 	outb(0x39, 0x03c4);
 	outb(1 << SLD0F3Val, 0x03c5);
 
@@ -295,7 +295,7 @@ void SetUMARam(void)
 	SLBase = (RamSize << 26) - (UmaSize << 20);
 
 	outb(0x6D, 0x03c4);
-	//SL Base[28:21] 
+	//SL Base[28:21]
 	outb((u8) ((SLBase >> 21) & 0xFF), 0x03c5);
 
 	outb(0x6e, 0x03c4);
diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c
index 3897e010b5..7bdc3418f1 100644
--- a/src/northbridge/via/vx800/vga.c
+++ b/src/northbridge/via/vx800/vga.c
@@ -62,19 +62,19 @@ static int via_vx800_int15_handler(struct eregs *regs)
 	case 0x5f18:
 	{
 		/*
-		 * BL Bit[7:4] 
-		 * Memory Data Rate 
-		 * 0000: 66MHz 
-		 * 0001: 100MHz 
-		 * 0010: 133MHz 
-		 * 0011: 200MHz ( DDR200 ) 
-		 * 0100: 266MHz ( DDR266 ) 
-		 * 0101: 333MHz ( DDR333 ) 
-		 * 0110: 400MHz ( DDR400 ) 
-		 * 0111: 533MHz ( DDR I/II 533 
+		 * BL Bit[7:4]
+		 * Memory Data Rate
+		 * 0000: 66MHz
+		 * 0001: 100MHz
+		 * 0010: 133MHz
+		 * 0011: 200MHz ( DDR200 )
+		 * 0100: 266MHz ( DDR266 )
+		 * 0101: 333MHz ( DDR333 )
+		 * 0110: 400MHz ( DDR400 )
+		 * 0111: 533MHz ( DDR I/II 533
 		 * 1000: 667MHz ( DDR I/II 667)
-		 * Bit[3:0]  
-		 * N:  Frame Buffer Size 2^N  MB 
+		 * Bit[3:0]
+		 * N:  Frame Buffer Size 2^N  MB
 		 */
 		u8 i;
 		device_t dev;
@@ -109,7 +109,7 @@ static int via_vx800_int15_handler(struct eregs *regs)
 	case 0x5f02:
 		regs->eax=0x5f;
 		regs->ebx= (regs->ebx & 0xffff0000) | 2;
-		regs->ecx= (regs->ecx & 0xffff0000) | 0x401;  // PAL + crt only 
+		regs->ecx= (regs->ecx & 0xffff0000) | 0x401;  // PAL + crt only
 		regs->edx= (regs->edx & 0xffff0000) | 0;  // TV Layout - default
 		res=0;
 		break;
@@ -118,7 +118,7 @@ static int via_vx800_int15_handler(struct eregs *regs)
 		res = 0;
 		break;
         default:
-		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", 
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
 				regs->eax & 0xffff);
 		regs->eax = 0;
 		break;
diff --git a/src/northbridge/via/vx800/vx800_early_serial.c b/src/northbridge/via/vx800/vx800_early_serial.c
index 6462a2d295..8bac43ff12 100644
--- a/src/northbridge/via/vx800/vx800_early_serial.c
+++ b/src/northbridge/via/vx800/vx800_early_serial.c
@@ -70,7 +70,7 @@ static void enable_vx800_serial(void)
 	// turn on pnp
 	vx800_writepnpaddr(0x87);
 	vx800_writepnpaddr(0x87);
-	// now go ahead and set up com1. 
+	// now go ahead and set up com1.
 	// set address
 	vx800_writepnpaddr(0x7);
 	vx800_writepnpdata(0x2);
diff --git a/src/northbridge/via/vx800/vx800_early_smbus.c b/src/northbridge/via/vx800/vx800_early_smbus.c
index 7ba9b41acb..e40d54d721 100644
--- a/src/northbridge/via/vx800/vx800_early_smbus.c
+++ b/src/northbridge/via/vx800/vx800_early_smbus.c
@@ -171,10 +171,10 @@ static void enable_smbus(void)
 }
 
 /**
- * A fixup for some systems that need time for the SMBus to "warm up". This is 
- * needed on some VT823x based systems, where the SMBus spurts out bad data for 
- * a short time after power on. This has been seen on the VIA Epia series and 
- * Jetway J7F2-series. It reads the ID byte from SMBus, looking for 
+ * A fixup for some systems that need time for the SMBus to "warm up". This is
+ * needed on some VT823x based systems, where the SMBus spurts out bad data for
+ * a short time after power on. This has been seen on the VIA Epia series and
+ * Jetway J7F2-series. It reads the ID byte from SMBus, looking for
  * known-good data from a slot/address. Exits on either good data or a timeout.
  *
  * TODO: This should probably go into some global file, but one would need to
diff --git a/src/northbridge/via/vx800/vx800_lpc.c b/src/northbridge/via/vx800/vx800_lpc.c
index 874f32fbbd..ce2d822946 100644
--- a/src/northbridge/via/vx800/vx800_lpc.c
+++ b/src/northbridge/via/vx800/vx800_lpc.c
@@ -42,9 +42,9 @@ static const unsigned char sd_ms_ctrl_Pins[4] = { 'B', 'C', 'D', 'A' };	//only I
 static const unsigned char ce_ata_nf_ctrl_Pins[4] = { 'C', 'C', 'D', 'A' };	//only INTA
 static const unsigned char idePins[4] = { 'B', 'C', 'D', 'A' };	//only INTA
 
-static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' };	//all 4 
+static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' };	//all 4
 
-static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' };	//only INTA 
+static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' };	//only INTA
 
 static unsigned char *pin_to_irq(const unsigned char *pin)
 {
@@ -218,7 +218,7 @@ static void S3_ps2_kb_ms_wakeup(struct device *dev)
 	pci_write_config8(dev, 0x51, enables);
 
 	outb(inb(VX800_ACPI_IO_BASE + 0x02) | 0x20, VX800_ACPI_IO_BASE + 0x02);	//ACPI golabe enable for sci smi trigger
-	outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x204, VX800_ACPI_IO_BASE + 0x22);	//ACPI SCI on Internal KBC PME and mouse PME  
+	outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x204, VX800_ACPI_IO_BASE + 0x22);	//ACPI SCI on Internal KBC PME and mouse PME
 
 }
 
@@ -354,17 +354,17 @@ static void southbridge_init(struct device *dev)
 		fadt->pm2_cnt_len = 1;//to support cpu-c3
 	#2
 		ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC )
-       #3    write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec. 
+       #3    write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec.
 	       1  enable SLP# asserts in C3 state  PMIORx26<1> =1
 		2    enable CPUSTP# asserts in C3 state;  PMIORx26<2> =1
 		3  CLKRUN# is always asserted  PMIORx26<3> =0
-		4    Disable PCISTP# When CLKRUN# is asserted 
-		1: PCISTP# will not assert When CLKRUN# is asserted 
+		4    Disable PCISTP# When CLKRUN# is asserted
+		1: PCISTP# will not assert When CLKRUN# is asserted
 		PMIORx26<4> =1
-		5  This bit controls whether the CPU voltage is lowered when in C3/S1 state.     
-		VRDSLP will be active in either this bit set in C3 or LVL4 register read 
+		5  This bit controls whether the CPU voltage is lowered when in C3/S1 state.
+		VRDSLP will be active in either this bit set in C3 or LVL4 register read
 		PMIORx26<0> =0
-		6  Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state  PMIORx15 
+		6  Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state  PMIORx15
 	*/
 	outb(0x17, VX800_ACPI_IO_BASE + 0x26);