diff options
| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-07-08 01:53:24 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-07-11 08:39:07 +0200 |
| commit | 7116ac803736345cc7c7b73ac435efa50c4cd2b0 (patch) | |
| tree | 64b7190ef4e61ba2e17a88c50e92c076c3aa2d19 /src/northbridge/via/vx800 | |
| parent | c805e62f9dd5e1b11906101845abd36b049e7dc3 (diff) | |
src: Make use of 'CEIL_DIV(a, b)' macro across tree
The objective here is to tighten coreboot up a bit by not repeating
common helpers. This makes the code base more consistent and
unified/tight.
Change-Id: Ia163eae68b4a84a00ed118125e70308fab1cea0c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6215
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/northbridge/via/vx800')
| -rw-r--r-- | src/northbridge/via/vx800/timing_setting.c | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/src/northbridge/via/vx800/timing_setting.c b/src/northbridge/via/vx800/timing_setting.c index df903049b9..3bd45e40ae 100644 --- a/src/northbridge/via/vx800/timing_setting.c +++ b/src/northbridge/via/vx800/timing_setting.c @@ -117,8 +117,7 @@ void SetTrp(DRAM_SYS_ATTR * DramAttr) /*Calculate clock,this value should be 2T,3T,4T,5T */ } Tmp = - (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - - 1) / ((DramAttr->DramCyc) << 2)); + (u16) CEIL_DIV(Max * 100, (DramAttr->DramCyc) << 2); PRINT_DEBUG_MEM("Trp = "); PRINT_DEBUG_MEM_HEX16(Tmp); PRINT_DEBUG_MEM("\r"); @@ -168,8 +167,7 @@ void SetTrcd(DRAM_SYS_ATTR * DramAttr) } /*Calculate clock,this value should be 2T,3T,4T,5T */ Tmp = - (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - - 1) / ((DramAttr->DramCyc) << 2)); + (u16) CEIL_DIV(Max * 100, (DramAttr->DramCyc) << 2); PRINT_DEBUG_MEM("Trcd ="); PRINT_DEBUG_MEM_HEX16(Tmp); PRINT_DEBUG_MEM("\r"); @@ -213,7 +211,7 @@ void SetTras(DRAM_SYS_ATTR * DramAttr) } /*Calculate clock,value range 5T-20T */ - Tmp = (u16) ((Max * 100 + DramAttr->DramCyc - 1) / (DramAttr->DramCyc)); + Tmp = (u16) CEIL_DIV((Max * 100), DramAttr->DramCyc); PRINT_DEBUG_MEM("Tras ="); PRINT_DEBUG_MEM_HEX16(Tmp); PRINT_DEBUG_MEM("\r"); @@ -288,7 +286,7 @@ void SetTrfc(DRAM_SYS_ATTR * DramAttr) } /*Calculate clock,value range 8T-71T */ - Tmp = (u16) ((Max + DramAttr->DramCyc - 1) / (DramAttr->DramCyc)); + Tmp = (u16) CEIL_DIV(Max, DramAttr->DramCyc); PRINT_DEBUG_MEM("Trfc = "); PRINT_DEBUG_MEM_HEX16(Tmp); PRINT_DEBUG_MEM("\r"); @@ -334,8 +332,7 @@ void SetTrrd(DRAM_SYS_ATTR * DramAttr) /*Calculate clock,this value should be 2T,3T,4T,5T */ Tmp = - (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - - 1) / ((DramAttr->DramCyc) << 2)); + (u16) CEIL_DIV(Max * 100, (DramAttr->DramCyc) << 2); PRINT_DEBUG_MEM("Trrd ="); PRINT_DEBUG_MEM_HEX16(Tmp); PRINT_DEBUG_MEM("\r"); @@ -378,7 +375,7 @@ void SetTwr(DRAM_SYS_ATTR * DramAttr) } } /*Calculate clock */ - Tmp = (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - 1) / ((DramAttr->DramCyc) << 2)); //this value should be 2T,3T,4T,5T + Tmp = (u16) CEIL_DIV((Max * 100), ((DramAttr->DramCyc) << 2)); //this value should be 2T,3T,4T,5T PRINT_DEBUG_MEM("Twr = "); PRINT_DEBUG_MEM_HEX16(Tmp); PRINT_DEBUG_MEM("\r"); @@ -421,7 +418,7 @@ void SetTwtr(DRAM_SYS_ATTR * DramAttr) } } /*Calculate clock */ - Tmp = (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - 1) / ((DramAttr->DramCyc) << 2)); //this value should be 2T or 3T + Tmp = (u16) CEIL_DIV((Max * 100), ((DramAttr->DramCyc) << 2)); //this value should be 2T or 3T PRINT_DEBUG_MEM("Twtr ="); PRINT_DEBUG_MEM_HEX16(Tmp); @@ -463,7 +460,7 @@ void SetTrtp(DRAM_SYS_ATTR * DramAttr) } } /*Calculate clock */ - Tmp = (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - 1) / ((DramAttr->DramCyc) << 2)); //this value should be 2T or 3T + Tmp = (u16) CEIL_DIV((Max * 100), ((DramAttr->DramCyc) << 2)); //this value should be 2T or 3T PRINT_DEBUG_MEM("Trtp ="); PRINT_DEBUG_MEM_HEX16(Tmp); |