diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2009-06-30 15:17:49 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2009-06-30 15:17:49 +0000 |
| commit | 0867062412dd4bfe5a556e5f3fd85ba5b682d79b (patch) | |
| tree | 81ca5db12b8567b48daaa23a541bfb8a5dc011f8 /src/northbridge/via/vx800 | |
| parent | 9702b6bf7ec5a4fb16934f1cf2724480e2460c89 (diff) | |
This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/via/vx800')
| -rw-r--r-- | src/northbridge/via/vx800/examples/cache_as_ram_auto.c | 8 | ||||
| -rw-r--r-- | src/northbridge/via/vx800/examples/chipset_init.c | 4 | ||||
| -rw-r--r-- | src/northbridge/via/vx800/romstrap.lds | 2 |
3 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/via/vx800/examples/cache_as_ram_auto.c b/src/northbridge/via/vx800/examples/cache_as_ram_auto.c index 8f53975f89..1580d48acb 100644 --- a/src/northbridge/via/vx800/examples/cache_as_ram_auto.c +++ b/src/northbridge/via/vx800/examples/cache_as_ram_auto.c @@ -563,7 +563,7 @@ the following code is copied from src\mainboard\tyan\s2735\cache_as_ram_auto.c Only the code around CLEAR_FIRST_1M_RAM is changed. I remove all the code around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c" the CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop at somewhere, -and cpu/x86/car/cache_as_ram_post.c do not cache my $XIP_ROM_BASE+SIZE area. +and cpu/x86/car/cache_as_ram_post.c do not cache my $CONFIG_XIP_ROM_BASE+SIZE area. So,I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c have some diff withx86-version */ @@ -621,11 +621,11 @@ So,I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c have #include "cpu/via/car/cache_as_ram_post.c" //#include "cpu/x86/car/cache_as_ram_post.c" __asm__ volatile ( - /* set new esp *//* before _RAMBASE */ + /* set new esp *//* before CONFIG_RAMBASE */ "subl %0, %%ebp\n\t" "subl %0, %%esp\n\t":: - "a" ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE) - - _RAMBASE) + "a" ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - + CONFIG_RAMBASE) ); { diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c index d4e7e40dec..644284eef7 100644 --- a/src/northbridge/via/vx800/examples/chipset_init.c +++ b/src/northbridge/via/vx800/examples/chipset_init.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 #include <arch/acpi.h> #endif #include <../northbridge/via/vx800/vx800.h> @@ -620,7 +620,7 @@ void init_VIA_chipset(void) void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 void *wake_vec; #endif diff --git a/src/northbridge/via/vx800/romstrap.lds b/src/northbridge/via/vx800/romstrap.lds index 2e300c95a5..66159e3a1c 100644 --- a/src/northbridge/via/vx800/romstrap.lds +++ b/src/northbridge/via/vx800/romstrap.lds @@ -19,7 +19,7 @@ */ SECTIONS { - . = (_ROMBASE + ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start); + . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) } |