geeesh! And this really compiles and even runs?

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 153 insertions, 210 deletions

diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c
index 08d3c95048..8cee44504b 100644
--- a/src/northbridge/via/vx800/examples/chipset_init.c
+++ b/src/northbridge/via/vx800/examples/chipset_init.c
@@ -43,12 +43,12 @@ static const struct VIA_PCI_REG_INIT_TABLE mSbStage1InitTbl[] = {
 	{0x00, 0xFF, SB_VLINK_REG(0xE6), 0xFF, 0x39},	// Enable SMM A-Seg, MSI and Io APIC
 	///// SPI-BAR.
 	//// SPI_BASE_ADDRESS = 0xFED1 0000
-	0x00, 0xFF, SB_LPC_REG(0xBC), 0xFF, 0x00,
-	0x00, 0xFF, SB_LPC_REG(0xBD), 0xFF, 0xD1,
-	0x00, 0xFF, SB_LPC_REG(0xBE), 0xFF, 0xFE,
-//      0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBC), 0xFF, 0x00,//this , for the different macro
-//      0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBD), 0xFF, 0xD1,
-//      0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBE), 0xFF, 0xFE,
+	{0x00, 0xFF, SB_LPC_REG(0xBC), 0xFF, 0x00},
+	{0x00, 0xFF, SB_LPC_REG(0xBD), 0xFF, 0xD1},
+	{0x00, 0xFF, SB_LPC_REG(0xBE), 0xFF, 0xFE},
+//      {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBC), 0xFF, 0x00},//this , for the different macro
+//      {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBD), 0xFF, 0xD1},
+//      {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBE), 0xFF, 0xFE},
 	///// End of 2008-04-17
 
 	{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	// End of Table
@@ -60,191 +60,184 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage2InitTable[] = {
 	// D0F2~D0F3 is configured by MemoryInit Peim
 
 	// D0F4: NB PMU
-	0x00, 0xFF, NB_PMU_REG(0x84), 0x00, 0xDB,
-	0x00, 0xFF, NB_PMU_REG(0x85), 0x00, 0x05,
-	0x00, 0xFF, NB_PMU_REG(0x89), 0x00, 0xF8,
-	0x00, 0xFF, NB_PMU_REG(0x8B), 0x00, 0xBF,
-	0x00, 0xFF, NB_PMU_REG(0x8D), 0x00, 0xFC,
-	0x00, 0xFF, NB_PMU_REG(0x8E), 0x00, 0x19,
-	0x00, 0xFF, NB_PMU_REG(0x8F), 0x03, 0x00,
-	0x00, 0xFF, NB_PMU_REG(0x90), 0x00, 0xFF,
-	0x00, 0xFF, NB_PMU_REG(0x91), 0x00, 0xFF,
-	0x00, 0xFF, NB_PMU_REG(0x92), 0x00, 0xCC,
-	0x00, 0xFF, NB_PMU_REG(0xA0), 0x00, 0x80,
-	0x00, 0xFF, NB_PMU_REG(0xA1), 0x00, 0xE0,
-	0x00, 0xFF, NB_PMU_REG(0xA2), 0x00, 0xD6,
-	0x00, 0xFF, NB_PMU_REG(0xA3), 0x00, 0x80,
-	0x00, 0xFF, NB_PMU_REG(0xA8), 0x00, 0x20,
+	{ 0x00, 0xFF, NB_PMU_REG(0x84), 0x00, 0xDB },
+	{ 0x00, 0xFF, NB_PMU_REG(0x85), 0x00, 0x05 },
+	{ 0x00, 0xFF, NB_PMU_REG(0x89), 0x00, 0xF8 },
+	{ 0x00, 0xFF, NB_PMU_REG(0x8B), 0x00, 0xBF },
+	{ 0x00, 0xFF, NB_PMU_REG(0x8D), 0x00, 0xFC },
+	{ 0x00, 0xFF, NB_PMU_REG(0x8E), 0x00, 0x19 },
+	{ 0x00, 0xFF, NB_PMU_REG(0x8F), 0x03, 0x00 },
+	{ 0x00, 0xFF, NB_PMU_REG(0x90), 0x00, 0xFF },
+	{ 0x00, 0xFF, NB_PMU_REG(0x91), 0x00, 0xFF },
+	{ 0x00, 0xFF, NB_PMU_REG(0x92), 0x00, 0xCC },
+	{ 0x00, 0xFF, NB_PMU_REG(0xA0), 0x00, 0x80 },
+	{ 0x00, 0xFF, NB_PMU_REG(0xA1), 0x00, 0xE0 },
+	{ 0x00, 0xFF, NB_PMU_REG(0xA2), 0x00, 0xD6 },
+	{ 0x00, 0xFF, NB_PMU_REG(0xA3), 0x00, 0x80 },
+	{ 0x00, 0xFF, NB_PMU_REG(0xA8), 0x00, 0x20 },
 
 	// D0F5: NB APIC, PXPTRF and MSGC
 	//Note: the Rx6A, RCRBH Base Address, is not set, which is related to PCIE Root Complex.
 	//Note: the Rx60, Extended CFG Address. Support and Rx61, Extended CFG Address, are set by NB Peim that is in the PEI Phase.
 	//Note: the Rx42, APIC Interrupt((BT_INTR)) Control, is set by NB Peim that is in PEI phase.
-	0x00, 0xFF, NB_PXPTRF_REG(0x50), 0x00, 0x00,
-	0x00, 0xFF, NB_PXPTRF_REG(0x54), 0x00, 0x80,
-	0x00, 0xFF, NB_PXPTRF_REG(0x55), 0x00, 0x04,
-	0x00, 0xFF, NB_PXPTRF_REG(0x58), 0x00, 0x00,
-	0x00, 0xFF, NB_PXPTRF_REG(0x59), 0x00, 0x02,
-	0x00, 0xFF, NB_PXPTRF_REG(0x5E), 0x00, 0x00,
-	0x00, 0xFF, NB_PXPTRF_REG(0x5F), 0x00, 0x06,
-	0x00, 0xFF, NB_PXPTRF_REG(0x80), 0x00, 0x18,	//Set RVC1DM, RTHBHIT, RUWRDYD, RUPRRDY1, RUWPOPHD to 1.
-	0x00, 0xFF, NB_PXPTRF_REG(0x82), 0x00, 0x00,	//Set RVC1RPSW, RVC1RQ1T to 1.
-	0x00, 0xFF, NB_PXPTRF_REG(0x83), 0x00, 0x81,
-	0x00, 0xFF, NB_PXPTRF_REG(0x84), 0x00, 0x28,
-	0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0xC0,
-	0x00, 0xFF, NB_MSGC_REG(0xA3), 0x00, 0x01,	// RWAKEEN
-//  0x00, 0xFF, NB_PXPTRF_REG(0x64), 0x40, 0x00, //RTDNP2B32EN
-	0x00, 0xFF, NB_PXPTRF_REG(0xF3), 0xFC, 0x20,
-	0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0x00,	//RP2P1ABORT
+	{ 0x00, 0xFF, NB_PXPTRF_REG(0x50), 0x00, 0x00 },
+	{ 0x00, 0xFF, NB_PXPTRF_REG(0x54), 0x00, 0x80 },
+	{ 0x00, 0xFF, NB_PXPTRF_REG(0x55), 0x00, 0x04 },
+	{ 0x00, 0xFF, NB_PXPTRF_REG(0x58), 0x00, 0x00 },
+	{ 0x00, 0xFF, NB_PXPTRF_REG(0x59), 0x00, 0x02 },
+	{ 0x00, 0xFF, NB_PXPTRF_REG(0x5E), 0x00, 0x00 },
+	{ 0x00, 0xFF, NB_PXPTRF_REG(0x5F), 0x00, 0x06 },
+	{ 0x00, 0xFF, NB_PXPTRF_REG(0x80), 0x00, 0x18 },	//Set RVC1DM, RTHBHIT, RUWRDYD, RUPRRDY1, RUWPOPHD to 1.
+	{ 0x00, 0xFF, NB_PXPTRF_REG(0x82), 0x00, 0x00 },	//Set RVC1RPSW, RVC1RQ1T to 1.
+	{ 0x00, 0xFF, NB_PXPTRF_REG(0x83), 0x00, 0x81 },
+	{ 0x00, 0xFF, NB_PXPTRF_REG(0x84), 0x00, 0x28 },
+	{ 0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0xC0 },
+	{ 0x00, 0xFF, NB_MSGC_REG(0xA3), 0x00, 0x01 },	// RWAKEEN
+	//{ 0x00, 0xFF, NB_PXPTRF_REG(0x64), 0x40, 0x00 }, //RTDNP2B32EN
+	{ 0x00, 0xFF, NB_PXPTRF_REG(0xF3), 0xFC, 0x20 },
+	{ 0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0x00 },	//RP2P1ABORT
 
 
 // fine-tune
 // If no settings, C7 will hang or reboot in XP, but CN will not.
-	0x00, 0xFF, NB_HOST_REG(0x51), 0x84, 0x00,
-	0x00, 0xFF, NB_HOST_REG(0x52), 0x0F, 0x03,
-	0x00, 0xFF, NB_HOST_REG(0x54), 0x04, 0x00,
-	0x00, 0xFF, NB_HOST_REG(0x55), 0x04, 0x00,
-	0x00, 0xFF, NB_HOST_REG(0x59), 0x09, 0x01,
-	0x00, 0xFF, NB_HOST_REG(0x5C), 0x10, 0x10,
-	0x00, 0xFF, NB_HOST_REG(0x5F), 0x0E, 0x08,
-	0x00, 0xFF, NB_HOST_REG(0x92), 0xFF, 0x04,	// ACPI Base addr
-	0x00, 0xFF, NB_HOST_REG(0x97), 0x01, 0x01,	// APIC MSI
-	0x00, 0xFF, NB_HOST_REG(0x99), 0x02, 0x00,	// APIC MSI
+	{ 0x00, 0xFF, NB_HOST_REG(0x51), 0x84, 0x00 },
+	{ 0x00, 0xFF, NB_HOST_REG(0x52), 0x0F, 0x03 },
+	{ 0x00, 0xFF, NB_HOST_REG(0x54), 0x04, 0x00 },
+	{ 0x00, 0xFF, NB_HOST_REG(0x55), 0x04, 0x00 },
+	{ 0x00, 0xFF, NB_HOST_REG(0x59), 0x09, 0x01 },
+	{ 0x00, 0xFF, NB_HOST_REG(0x5C), 0x10, 0x10 },
+	{ 0x00, 0xFF, NB_HOST_REG(0x5F), 0x0E, 0x08 },
+	{ 0x00, 0xFF, NB_HOST_REG(0x92), 0xFF, 0x04 },	// ACPI Base addr
+	{ 0x00, 0xFF, NB_HOST_REG(0x97), 0x01, 0x01 },	// APIC MSI
+	{ 0x00, 0xFF, NB_HOST_REG(0x99), 0x02, 0x00 },	// APIC MSI
 	//GTL
-	0x00, 0xFF, NB_HOST_REG(0x73), 0xFF, 0x66,
-	0x00, 0xFF, NB_HOST_REG(0xB2), 0xFF, 0x33,
-	0x00, 0xFF, NB_HOST_REG(0xB3), 0xFF, 0x33,
-	0x00, 0xFF, NB_HOST_REG(0xBC), 0xFF, 0x33,
-	0x00, 0xFF, NB_HOST_REG(0xBD), 0xFF, 0x33,
-	0x00, 0xFF, NB_HOST_REG(0xC5), 0x30, 0x20,
-	0x00, 0xFF, NB_HOST_REG(0xC8), 0x10, 0x00,
+	{ 0x00, 0xFF, NB_HOST_REG(0x73), 0xFF, 0x66 },
+	{ 0x00, 0xFF, NB_HOST_REG(0xB2), 0xFF, 0x33 },
+	{ 0x00, 0xFF, NB_HOST_REG(0xB3), 0xFF, 0x33 },
+	{ 0x00, 0xFF, NB_HOST_REG(0xBC), 0xFF, 0x33 },
+	{ 0x00, 0xFF, NB_HOST_REG(0xBD), 0xFF, 0x33 },
+	{ 0x00, 0xFF, NB_HOST_REG(0xC5), 0x30, 0x20 },
+	{ 0x00, 0xFF, NB_HOST_REG(0xC8), 0x10, 0x00 },
 
 
 	// End of Table
 	{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	// End of Table
-
 };
 
 static const struct VIA_PCI_REG_INIT_TABLE mBusControllerInitTable[] = {
 	// D17F0: LPC
-	0x00, 0xFF, SB_LPC_REG(0x40), 0x44, 0x44,	//  Enable I/O Recovery Time,  4D0/4D1 Support
-	0x00, 0xFF, SB_LPC_REG(0x42), 0xF8, 0xF0,	//  ENLBUF, GINTREN, FLUSHEN, RBRSTRD
-	0x00, 0xFF, SB_LPC_REG(0x43), 0x0F, 0x0B,	//  RENDTX, ENWBTO, ENRBTO
-	//  0x00, 0xFF, SB_LPC_REG(0x46), 0x00, 0x10,     // It is related to INTH#
-	//0x00, 0xFF, SB_LPC_REG(0x48), 0x00, 0x0C,      //RMRPW, RIRPW  // Reserved in 409 by Eric
+	{ 0x00, 0xFF, SB_LPC_REG(0x40), 0x44, 0x44 },	//  Enable I/O Recovery Time,  4D0/4D1 Support
+	{ 0x00, 0xFF, SB_LPC_REG(0x42), 0xF8, 0xF0 },	//  ENLBUF, GINTREN, FLUSHEN, RBRSTRD
+	{ 0x00, 0xFF, SB_LPC_REG(0x43), 0x0F, 0x0B },	//  RENDTX, ENWBTO, ENRBTO
+	//{ 0x00, 0xFF, SB_LPC_REG(0x46), 0x00, 0x10 },     // It is related to INTH#
+	//{ 0x00, 0xFF, SB_LPC_REG(0x48), 0x00, 0x0C },      //RMRPW, RIRPW  // Reserved in 409 by Eric
 
 	// Internal RTC, Mouse, Keyboard // set in PEI by Eric
-	//0x00, 0xFF, SB_LPC_REG(0x51), 0x10, 0x0D,      // Enable Internal RTC, Internal PS2 Mouse/Keyboard
+	//{ 0x00, 0xFF, SB_LPC_REG(0x51), 0x10, 0x0D },      // Enable Internal RTC, Internal PS2 Mouse/Keyboard
 
 	// RTC
-	0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x01,	//RTC Rx32 Map to Centrury Byte
+	{ 0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x01 },	//RTC Rx32 Map to Centrury Byte
 
-	// 0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x02,    // RDMEGAS
-	//0x00, 0xFF, SB_LPC_REG(0x4E), 0x00, 0x08,  // Enable RTC port 74/75, ENEXRTC // set in PEI by Eric
+	//{ 0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x02 },    // RDMEGAS
+	//{ 0x00, 0xFF, SB_LPC_REG(0x4E), 0x00, 0x08 },  // Enable RTC port 74/75, ENEXRTC // set in PEI by Eric
 
 	// Serial IRQ  // set in PEI by Eric
-	//0x00, 0xFF, SB_LPC_REG(0x52), 0x0F, 0x09,    // Enable Serial IRQ, Start Frame Width is 6 PCI Clock.
+	//{ 0x00, 0xFF, SB_LPC_REG(0x52), 0x0F, 0x09 },    // Enable Serial IRQ, Start Frame Width is 6 PCI Clock.
 
 	// Enable 4D0h/4D1h Port
-	//0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x04,    // EISAXT // set in PEI by Eric
+	//{ 0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x04 },    // EISAXT // set in PEI by Eric
 
 	// Config ROM Interface
 	// Enable SPI/Set SPI Memory Base Address
 	// It is initialized in PEI Phase
 
 	// Subsystem ID/Vendor ID Back Door
-	0x00, 0xFF, SB_LPC_REG(0x70), 0xFF, 0x06,
-	0x00, 0xFF, SB_LPC_REG(0x71), 0xFF, 0x11,
-	0x00, 0xFF, SB_LPC_REG(0x72), 0xFF, 0x09,
-	0x00, 0xFF, SB_LPC_REG(0x73), 0xFF, 0x34,
+	{ 0x00, 0xFF, SB_LPC_REG(0x70), 0xFF, 0x06 },
+	{ 0x00, 0xFF, SB_LPC_REG(0x71), 0xFF, 0x11 },
+	{ 0x00, 0xFF, SB_LPC_REG(0x72), 0xFF, 0x09 },
+	{ 0x00, 0xFF, SB_LPC_REG(0x73), 0xFF, 0x34 },
 
-	0x00, 0xFF, SB_LPC_REG(0x4C), 0xC0, 0x40,
-	0x00, 0xFF, SB_LPC_REG(0x5B), 0x00, 0x51,	// Orgin value 0x53, modify for 409 by Eric
-	0x00, 0xFF, SB_LPC_REG(0x67), 0x03, 0x01,
+	{ 0x00, 0xFF, SB_LPC_REG(0x4C), 0xC0, 0x40 },
+	{ 0x00, 0xFF, SB_LPC_REG(0x5B), 0x00, 0x51 },	// Orgin value 0x53, modify for 409 by Eric
+	{ 0x00, 0xFF, SB_LPC_REG(0x67), 0x03, 0x01 },
 
 
-	0x00, 0xFF, SB_LPC_REG(0x50), 0x7E, 0x00,	// Setting PCI device enable
-	0x00, 0xFF, SB_LPC_REG(0x51), 0xD0, 0x00,	// Setting PCI device enable
-	0x00, 0xFF, SB_VLINK_REG(0xD1), 0x04, 0x00,	// Setting HDAC enable
+	{ 0x00, 0xFF, SB_LPC_REG(0x50), 0x7E, 0x00 },	// Setting PCI device enable
+	{ 0x00, 0xFF, SB_LPC_REG(0x51), 0xD0, 0x00 },	// Setting PCI device enable
+	{ 0x00, 0xFF, SB_VLINK_REG(0xD1), 0x04, 0x00 },	// Setting HDAC enable
 	{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	// End of Table
 };
 
 static const struct VIA_PCI_REG_INIT_TABLE mPCI1InitTable[] = {
 	//PCI1 Programming Sequence
 	//(1)Configure D17F7
-	0x00, 0xFF, SB_VLINK_REG(0x04), 0x00, 0x03,
-	0x00, 0xFF, SB_VLINK_REG(0x0C), 0x00, 0x08,	// Reserved in 409 by Eric
-	0x00, 0xFF, SB_VLINK_REG(0x4F), 0x40, 0x41,	//RENPPB, RP2CFLSH
-	0x00, 0xFF, SB_VLINK_REG(0x77), 0x00, 0x48,	//ROP2CFLSH, RFFTMR[1:0]. ROP2CFLSH work with Rx4F[0](RP2CFLSH) assertion
-	// 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x80,      //RSUB_DEC_P2P, RSUBDECOD(Window xp). If Bit7 is set, PCI lock will occured.
-	//0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x81,      //RSUB_DEC_P2P, RSUBDECOD(Window Vista)
+	{ 0x00, 0xFF, SB_VLINK_REG(0x04), 0x00, 0x03 },
+	{ 0x00, 0xFF, SB_VLINK_REG(0x0C), 0x00, 0x08 },	// Reserved in 409 by Eric
+	{ 0x00, 0xFF, SB_VLINK_REG(0x4F), 0x40, 0x41 },	//RENPPB, RP2CFLSH
+	{ 0x00, 0xFF, SB_VLINK_REG(0x77), 0x00, 0x48 },	//ROP2CFLSH, RFFTMR[1:0]. ROP2CFLSH work with Rx4F[0](RP2CFLSH) assertion
+	// { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x80 },      //RSUB_DEC_P2P, RSUBDECOD(Window xp). If Bit7 is set, PCI lock will occured.
+	// { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x81 },      //RSUB_DEC_P2P, RSUBDECOD(Window Vista)
 	//(2)Configure D19F0
-	0x00, 0xFF, SB_P2PB_REG(0x04), 0x00, 0x07,
+	{ 0x00, 0xFF, SB_P2PB_REG(0x04), 0x00, 0x07 },
 
 	//(3)Performance Recommended Setting
 
 	//Save Power
-	0x00, 0xFF, SB_VLINK_REG(0xE2), 0x1F, 0x01,
-	0x00, 0xFF, SB_VLINK_REG(0xE3), 0xF1, 0x5E,
-	0x00, 0xFF, SB_VLINK_REG(0x74), 0x40, 0x00,
+	{ 0x00, 0xFF, SB_VLINK_REG(0xE2), 0x1F, 0x01 },
+	{ 0x00, 0xFF, SB_VLINK_REG(0xE3), 0xF1, 0x5E },
+	{ 0x00, 0xFF, SB_VLINK_REG(0x74), 0x40, 0x00 },
 	//Enhence Host To PCI cycle performance and PCI-To-Host Cycle performance
-	0x00, 0xFF, SB_VLINK_REG(0x70), 0x00, 0x82,
-	0x00, 0xFF, SB_VLINK_REG(0x71), 0x30, 0xC0,
-	0x00, 0xFF, SB_VLINK_REG(0x72), 0x00, 0xEE,
+	{ 0x00, 0xFF, SB_VLINK_REG(0x70), 0x00, 0x82 },
+	{ 0x00, 0xFF, SB_VLINK_REG(0x71), 0x30, 0xC0 },
+	{ 0x00, 0xFF, SB_VLINK_REG(0x72), 0x00, 0xEE },
 
 	//Cycle Control
-	0x00, 0xFF, SB_VLINK_REG(0x73), 0x00, 0x01,
-	0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x0C,
+	{ 0x00, 0xFF, SB_VLINK_REG(0x73), 0x00, 0x01 },
+	{ 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x0C },
 	//Arbitration control
-	0x00, 0xFF, SB_VLINK_REG(0x75), 0x00, 0x0F,
-	0x00, 0xFF, SB_VLINK_REG(0x76), 0x00, 0xD0,
+	{ 0x00, 0xFF, SB_VLINK_REG(0x75), 0x00, 0x0F },
+	{ 0x00, 0xFF, SB_VLINK_REG(0x76), 0x00, 0xD0 },
 	{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	// End of Table
 };
 
 static const struct VIA_PCI_REG_INIT_TABLE mCCAInitTable[] = {
-
-	0x00, 0xFF, SB_VLINK_REG(0xFC), 0x02, 0x08,	//RVWREQ, ROABKDOOR
+	{ 0x00, 0xFF, SB_VLINK_REG(0xFC), 0x02, 0x08 },	//RVWREQ, ROABKDOOR
 
 	//CCA's Register Programming sequence
-	0x00, 0xFF, SB_VLINK_REG(0x50), 0x00, 0x08,	//Config Azalia's upstream cycle high priority and other low priority
-	0x00, 0xFF, SB_VLINK_REG(0x51), 0x40, 0x80,	//Disable bypass asynchronous circuit
-	0x00, 0xFF, SB_VLINK_REG(0x52), 0x00, 0x11,	// Set SM Internal Device and HDAC Occupy Timer
-	0x00, 0xFF, SB_VLINK_REG(0x53), 0x00, 0x11,	// Set SM Internal Device and HDAC Promote Timer
-	0x00, 0xFF, SB_VLINK_REG(0x54), 0xFF, 0x02,	//Use SB internal devices's original REQ
-	0x00, 0xFF, SB_VLINK_REG(0x73), 0x10, 0x00,	//RPINOWSC. Enable APIC Cycle Block P2C Write Cycle
-	0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x3C,	//RLCKXP2C, RFSBVK.
-	0x00, 0xFF, SB_VLINK_REG(0xE1), 0x07, 0x00,	//RBLKAPIC, RAZC3
-	0x00, 0xFF, SB_VLINK_REG(0x7C), 0x04, 0x02,	//RNMIFSB, RFSBVK
-	0x00, 0xFF, SB_VLINK_REG(0xE0), 0xF0, 0x90,	//RCCA_NEWCLK, RCCA_CLKON. Use New dynamic clock scheme
-	0x00, 0xFF, SB_VLINK_REG(0xE7), 0xFF, 0x00,	//Let CCA use dynamic clock.
+	{ 0x00, 0xFF, SB_VLINK_REG(0x50), 0x00, 0x08 },	//Config Azalia's upstream cycle high priority and other low priority
+	{ 0x00, 0xFF, SB_VLINK_REG(0x51), 0x40, 0x80 },	//Disable bypass asynchronous circuit
+	{ 0x00, 0xFF, SB_VLINK_REG(0x52), 0x00, 0x11 },	// Set SM Internal Device and HDAC Occupy Timer
+	{ 0x00, 0xFF, SB_VLINK_REG(0x53), 0x00, 0x11 },	// Set SM Internal Device and HDAC Promote Timer
+	{ 0x00, 0xFF, SB_VLINK_REG(0x54), 0xFF, 0x02 },	//Use SB internal devices's original REQ
+	{ 0x00, 0xFF, SB_VLINK_REG(0x73), 0x10, 0x00 },	//RPINOWSC. Enable APIC Cycle Block P2C Write Cycle
+	{ 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x3C },	//RLCKXP2C, RFSBVK.
+	{ 0x00, 0xFF, SB_VLINK_REG(0xE1), 0x07, 0x00 },	//RBLKAPIC, RAZC3
+	{ 0x00, 0xFF, SB_VLINK_REG(0x7C), 0x04, 0x02 },	//RNMIFSB, RFSBVK
+	{ 0x00, 0xFF, SB_VLINK_REG(0xE0), 0xF0, 0x90 },	//RCCA_NEWCLK, RCCA_CLKON. Use New dynamic clock scheme
+	{ 0x00, 0xFF, SB_VLINK_REG(0xE7), 0xFF, 0x00 },	//Let CCA use dynamic clock.
 	//The CCA is also relate to D17F0
-	//    0x00, 0xFF, SB_LPC_REG(0x49), 0x1F, 0x00,       //Disable CCA Test Mode
-	0x00, 0xFF, SB_LPC_REG(0x74), 0xFF, 0x00,	// Let DMA cycles from internal devices directly go to NB // Reserved in 409 by Eric
+	//{ 0x00, 0xFF, SB_LPC_REG(0x49), 0x1F, 0x00 },       //Disable CCA Test Mode
+	{ 0x00, 0xFF, SB_LPC_REG(0x74), 0xFF, 0x00 },	// Let DMA cycles from internal devices directly go to NB // Reserved in 409 by Eric
 	{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	// End of Table
 };
 
 static const struct VIA_PCI_REG_INIT_TABLE IDEC_INIT[] = {
-
-	// 0x00, 0xFF, SB_IDEC_REG(0x09), 0x00, 0x05, //set to native mode
-	0x00, 0xFF, SB_IDEC_REG(0x04), 0x00, 0x07,
-	//0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F,
+	//{0x00, 0xFF, SB_IDEC_REG(0x09), 0x00, 0x05}, //set to native mode
+	{0x00, 0xFF, SB_IDEC_REG(0x04), 0x00, 0x07},
+	//{0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F},
 	{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	// End of Table
-
 };
 
 static const struct VIA_PCI_REG_INIT_TABLE mSbApicInitTable[] = {
-	0x00, 0xFF, SB_LPC_REG(0x4D), 0x04, 0x00,
-	0x00, 0xFF, SB_LPC_REG(0x5B), 0x0E, 0x00,
-	0x00, 0xFF, SB_LPC_REG(0x6C), 0x08, 0x00,
-	0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x40,
-	0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x04,
-	//0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F,
-	{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	// End of Table
-
+	{ 0x00, 0xFF, SB_LPC_REG(0x4D), 0x04, 0x00 },
+	{ 0x00, 0xFF, SB_LPC_REG(0x5B), 0x0E, 0x00 },
+	{ 0x00, 0xFF, SB_LPC_REG(0x6C), 0x08, 0x00 },
+	{ 0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x40 },
+	{ 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x04 },
+	//{ 0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F },
+	{ 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },	// End of Table
 };
 
-
-
 void AcpiInit(void)
 {
 	device_t_raw rawdevice = 0;
@@ -268,10 +261,8 @@ void AcpiInit(void)
 
 	// Close all SMI/Io Traps
 	outb(0x00, VX800_ACPI_IO_BASE + 0x42);
-
 }
 
-
 void Stage2NbInit(void)
 {
 	device_t_raw rawdevice = 0;
@@ -290,7 +281,6 @@ void Stage2NbInit(void)
 
 	//vx855 NB no pcie bus
 	//vx855 NB no apic
-
 }
 
 void IDECSupportOption(u8 sbchiprev)
@@ -313,7 +303,6 @@ void InitIDEC(u8 sbchiprev)
 	IDECSupportOption(sbchiprev);
 }
 
-
 void InitUHCI(u8 Number, u8 bEnable)
 {
 	u8 Mask, Value;
@@ -374,25 +363,24 @@ void InitUHCI(u8 Number, u8 bEnable)
 
 static const struct VIA_PCI_REG_INIT_TABLE mEHCIInitTable[] = {
 	//EHCI
-	0x00, 0xFF, SB_EHCI_REG(0x43), 0x00, 0xC0,
-	0x00, 0xFF, SB_EHCI_REG(0x50), 0x00, 0x80,
-	0x00, 0xFF, SB_EHCI_REG(0x48), 0x20, 0x9E,
-	0x00, 0xFF, SB_EHCI_REG(0x49), 0x10, 0x68,
-	0x00, 0xFF, SB_EHCI_REG(0x4B), 0x00, 0x69,
-	0x00, 0xFF, SB_EHCI_REG(0x4D), 0x00, 0x94,
-	0x00, 0xFF, SB_EHCI_REG(0x52), 0x08, 0x00,
-	0x00, 0xFF, SB_EHCI_REG(0x5A), 0x00, 0x8A,
-	0x00, 0xFF, SB_EHCI_REG(0x5B), 0x00, 0x89,
-	0x00, 0xFF, SB_EHCI_REG(0x5C), 0x00, 0x03,
-	0x00, 0xFF, SB_EHCI_REG(0x5D), 0x00, 0x9A,
-	0x00, 0xFF, SB_EHCI_REG(0x5E), 0x00, 0x00,
-	0x00, 0xFF, SB_EHCI_REG(0x6B), 0x00, 0x00,
-	0x00, 0xFF, SB_EHCI_REG(0x6D), 0x00, 0x00,
-	0x00, 0xFF, SB_EHCI_REG(0x6F), 0xF0, 0x00,
-	0x00, 0xFF, SB_EHCI_REG(0x4E), 0x01, 0x01,
-	0x00, 0xFF, SB_EHCI_REG(0x4F), 0x00, 0x11,
-	{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	// End of Table
-
+	{ 0x00, 0xFF, SB_EHCI_REG(0x43), 0x00, 0xC0 },
+	{ 0x00, 0xFF, SB_EHCI_REG(0x50), 0x00, 0x80 },
+	{ 0x00, 0xFF, SB_EHCI_REG(0x48), 0x20, 0x9E },
+	{ 0x00, 0xFF, SB_EHCI_REG(0x49), 0x10, 0x68 },
+	{ 0x00, 0xFF, SB_EHCI_REG(0x4B), 0x00, 0x69 },
+	{ 0x00, 0xFF, SB_EHCI_REG(0x4D), 0x00, 0x94 },
+	{ 0x00, 0xFF, SB_EHCI_REG(0x52), 0x08, 0x00 },
+	{ 0x00, 0xFF, SB_EHCI_REG(0x5A), 0x00, 0x8A },
+	{ 0x00, 0xFF, SB_EHCI_REG(0x5B), 0x00, 0x89 },
+	{ 0x00, 0xFF, SB_EHCI_REG(0x5C), 0x00, 0x03 },
+	{ 0x00, 0xFF, SB_EHCI_REG(0x5D), 0x00, 0x9A },
+	{ 0x00, 0xFF, SB_EHCI_REG(0x5E), 0x00, 0x00 },
+	{ 0x00, 0xFF, SB_EHCI_REG(0x6B), 0x00, 0x00 },
+	{ 0x00, 0xFF, SB_EHCI_REG(0x6D), 0x00, 0x00 },
+	{ 0x00, 0xFF, SB_EHCI_REG(0x6F), 0xF0, 0x00 },
+	{ 0x00, 0xFF, SB_EHCI_REG(0x4E), 0x01, 0x01 },
+	{ 0x00, 0xFF, SB_EHCI_REG(0x4F), 0x00, 0x11 },
+	{ 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },	// End of Table
 };
 
 void InitEHCI(u8 Number, u8 bEnable)
@@ -483,23 +471,23 @@ void HpetInit(void)
 
 static const struct VIA_PCI_REG_INIT_TABLE mPMUInitTable[] = {
 	// Power Management
-	0x00, 0xFF, SB_LPC_REG(0x80), 0x00, 0x20,
-	0x00, 0xFF, SB_LPC_REG(0x8C), 0x02, 0x00,
-	0x00, 0xFF, SB_LPC_REG(0x8D), 0x00, 0x18,
+	{ 0x00, 0xFF, SB_LPC_REG(0x80), 0x00, 0x20 },
+	{ 0x00, 0xFF, SB_LPC_REG(0x8C), 0x02, 0x00 },
+	{ 0x00, 0xFF, SB_LPC_REG(0x8D), 0x00, 0x18 },
 
 	//Miscellaneous Configuration 1
-	0x00, 0xFF, SB_LPC_REG(0x94), 0xF0, 0x28,
-	0x00, 0xFF, SB_LPC_REG(0x95), 0x00, 0xC1,
-	0x00, 0xFF, SB_LPC_REG(0x96), 0xFF, 0x10,
-	0x00, 0xFF, SB_LPC_REG(0x97), 0x00, 0xB2,
+	{ 0x00, 0xFF, SB_LPC_REG(0x94), 0xF0, 0x28 },
+	{ 0x00, 0xFF, SB_LPC_REG(0x95), 0x00, 0xC1 },
+	{ 0x00, 0xFF, SB_LPC_REG(0x96), 0xFF, 0x10 },
+	{ 0x00, 0xFF, SB_LPC_REG(0x97), 0x00, 0xB2 },
 
 	//Voltage Change Function Enable
-	0x00, 0xFF, SB_LPC_REG(0x9F), 0x00, 0x21,
+	{ 0x00, 0xFF, SB_LPC_REG(0x9F), 0x00, 0x21 },
 	//Internal PCIe and NM PLL Control
-	0x00, 0xFF, SB_LPC_REG(0xE2), 0x00, 0xEA,
+	{ 0x00, 0xFF, SB_LPC_REG(0xE2), 0x00, 0xEA },
 
-	0x00, 0xFF, SB_LPC_REG(0xE7), 0x00, 0x80,
-	{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	// End of Table
+	{ 0x00, 0xFF, SB_LPC_REG(0xE7), 0x00, 0x80 },
+	{ 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },	// End of Table
 };
 
 void InitPMU(u8 sbchiprev)
@@ -589,7 +577,6 @@ void Stage2SbInit(void)
 
 }
 
-
 void init_VIA_chipset(void)
 {
 	printk(BIOS_DEBUG, "In: init_VIA_chipset\n");
@@ -633,7 +620,6 @@ void hardwaremain(int boot_complete)
 	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 #if 0
-
 	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xa3, 0x80);
 	pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0x60, 0x20);
 	pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0xE5,
@@ -656,7 +642,6 @@ void hardwaremain(int boot_complete)
 	printk(BIOS_INFO, "=================SB 50h=%02x \n",
 		    pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x50));
 
-
 	/* FIXME: Is there a better way to handle this? */
 	init_timer();
 	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
@@ -690,9 +675,7 @@ void hardwaremain(int boot_complete)
 		y = 0;
 		for (; y < 16; y++) {
 			printk(BIOS_INFO, "%02x ",
-				    pci_rawread_config8(PCI_RAWDEV
-							(0, 0x10, 4),
-							x * 16 + y));
+			   pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y));
 		}
 		printk(BIOS_INFO, "\n");
 	}
@@ -710,9 +693,7 @@ void hardwaremain(int boot_complete)
 		y = 0;
 		for (; y < 16; y++) {
 			printk(BIOS_INFO, "%02x ",
-				    pci_rawread_config8(PCI_RAWDEV
-							(0, 0x10, 4),
-							x * 16 + y));
+			    pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y));
 		}
 		printk(BIOS_INFO, "\n");
 	}
@@ -722,7 +703,6 @@ void hardwaremain(int boot_complete)
 	post_code(0x89);
 	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
-
 //          pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, 0x0571);
 
 #if 0
@@ -732,17 +712,13 @@ void hardwaremain(int boot_complete)
 		y = 0;
 		for (; y < 16; y++) {
 			printk(BIOS_INFO, "%02x ",
-				    pci_rawread_config8(PCI_RAWDEV
-							(0, 0x10, 4),
-							x * 16 + y));
+			    pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y));
 		}
 		printk(BIOS_INFO, "\n");
 	}
 #endif
 
-
 #if 0
-
 	y = pci_rawread_config8(PCI_RAWDEV(0, 0xf, 0), 0x0d);
 	y &= 0x0f;
 	y |= 0x40;
@@ -750,8 +726,6 @@ void hardwaremain(int boot_complete)
 #endif
 
 #if 0
-
-
 	static const d0f0pcitable[5] = { 0xD0, 0, 0, 0, 0xFD };
 	static const d0f2pcitable[16 * 7 + 1] = {
 		0x88, 0xF8, 0xEF, 0x44, 0x7C, 0x24, 0x63, 0x01, 0x00, 0x09,
@@ -911,7 +885,6 @@ void hardwaremain(int boot_complete)
 		    0x00, 0x00, 0x48, 0x00, 0x00, 0x00,
 	};
 
-
 #define OPTION_1 1
 #define NOOPTION_1 1
 #ifdef OPTION_1
@@ -943,24 +916,19 @@ void hardwaremain(int boot_complete)
 	};
 #endif
 
-
-
 	u8 i;
 /* error form ---- but add the chance to resume
-for(i=0;i<5;i++){
+	for(i=0;i<5;i++) {
 		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i, d0f0pcitable[i+0xcb]);
 	}
-
-
 */
 
 /* RO reg
-for(i=0;i<5;i++){
+	for(i=0;i<5;i++) {
 		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i+0xcb, d0f0pcitable[i]);
 	}
 */
 
-
 //boot ok, resume still err in linux
 #if 1
 	for (i = 0; i < 9; i++) {
@@ -1052,11 +1020,7 @@ for(i=0;i<5;i++){
 
 //d15f0
 
-
-
-
 #if 1
-
 	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 0), 0x4a, 0xa2);	// no affect.
 	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 1), 0x4a, 0xa2);
 	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 2), 0x4a, 0xa2);
@@ -1077,8 +1041,6 @@ for(i=0;i<5;i++){
 	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6f, 0x80);
 #endif
 
-
-
 #if 1
 //before (11.0)is add, s3 resume has already always dead in first resume(more frequenly), and sleep ok
 //      for(i=0;i<192;i++){
@@ -1094,7 +1056,6 @@ for(i=0;i<5;i++){
 				     d11f0pcitable[i]);
 	}
 
-
 	for (i = 18; i < 21; i++) {	//sleep ok ,   sleep err 1, resume
 		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
@@ -1225,7 +1186,6 @@ for(i=0;i<5;i++){
 	pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0x72,
 			      PCI_DEVICE_ID_VIA_VX855_LPC);
 
-
 //boot ok, resume still err in linux
 	for (i = 0; i < 192; i++) {
 		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), i + 0x40,
@@ -1240,17 +1200,12 @@ for(i=0;i<5;i++){
 	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x88, 0x02);
 	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0xe6, 0x3f);
 #endif
-
 	pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x20);
 	pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x41, 0x31);
 
-
-
 #ifdef OPTION_1
 	pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x00);
 #endif
-
-
 #endif
 
 	u8 i911;
@@ -1262,10 +1217,9 @@ for(i=0;i<5;i++){
 	i911 |= 0x01;
 	pci_rawwrite_config8(PCI_RAWDEV(0, 0x1, 0), 0xb0, i911);
 
-
 #if 1
 	struct device *dev;
-	printk(BIOS_INFO, "=========zjldump all  devices...\n");
+	printk(BIOS_INFO, "========= dump all  devices...\n");
 	for (dev = all_devices; dev; dev = dev->next) {
 		if (dev->path.type == DEVICE_PATH_PCI) {
 			printk(BIOS_DEBUG, "%s dump\n", dev_path(dev));
@@ -1274,25 +1228,14 @@ for(i=0;i<5;i++){
 				y = 0;
 				for (; y < 16; y++) {
 					printk(BIOS_INFO, "%02x ",
-						    pci_read_config8(dev,
-								     x *
-								     16 +
-								     y));
+					    pci_read_config8(dev, x * 16 + y));
 				}
 				printk(BIOS_INFO, "\n");
 			}
-
 		}
 		printk(BIOS_INFO, "\n");
 	}
 #endif
-
-
-
-
 	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x04, 0x17, 0x17);//
-//      pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x0c, 0x08, 0xff);///
-
-
-
+	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x0c, 0x08, 0xff);///
 }