diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-05 21:02:23 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-09 21:36:47 +0200 |
| commit | e7aeb2f60212077521f7d71a4f485c8f4a26f6c6 (patch) | |
| tree | 2c9b89bd9d2bd173aaee4f7e36e65217573d1fc7 /src/northbridge/via/vx800/driving_clk_phase_data.h | |
| parent | 83b9703505becf34728a2286a3ad3e6749a4d619 (diff) | |
src/northbridge/via: Remove commented code
Change-Id: Ic589b26c6c94df12e1fe218d079018db8b38fbd9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16898
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/via/vx800/driving_clk_phase_data.h')
| -rw-r--r-- | src/northbridge/via/vx800/driving_clk_phase_data.h | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/src/northbridge/via/vx800/driving_clk_phase_data.h b/src/northbridge/via/vx800/driving_clk_phase_data.h index e9190fac30..b77c593e8f 100644 --- a/src/northbridge/via/vx800/driving_clk_phase_data.h +++ b/src/northbridge/via/vx800/driving_clk_phase_data.h @@ -16,51 +16,19 @@ #ifndef DRIVINGCLKPHASEDATA_H #define DRIVINGCLKPHASEDATA_H -//extern u8 DDR2_DQSA_Driving_Table[4]; -//extern u8 DDR2_DQSB_Driving_Table[2]; - -//extern u8 DDR2_DQA_Driving_Table[4]; -//extern u8 DDR2_DQB_Driving_Table[2]; - -//extern u8 DDR2_CSA_Driving_Table_x8[4]; -//extern u8 DDR2_CSB_Driving_Table_x8[2]; -//extern u8 DDR2_CSA_Driving_Table_x16[4]; -//extern u8 DDR2_CSB_Driving_Table_x16[2]; - #define MA_Table 3 -//extern u8 DDR2_MAA_Driving_Table[MA_Table][4]; -//extern u8 DDR2_MAB_Driving_Table[MA_Table][2]; - -//extern u8 DDR2_DCLKA_Driving_Table[4]; -//extern u8 DDR2_DCLKB_Driving_Table[4]; #define DUTY_CYCLE_FREQ_NUM 6 #define DUTY_CYCLE_REG_NUM 3 -//extern u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM]; -//extern u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM]; #define Clk_Phase_Table_DDR2_Width 6 -//extern u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width]; -//extern u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width]; -//extern u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width]; #define WrtData_REG_NUM 4 #define WrtData_FREQ_NUM 6 -//extern u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM]; -//extern u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM]; #define DQ_DQS_Delay_Table_Width 4 -//extern u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width]; -//extern u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width]; #define DQS_INPUT_CAPTURE_REG_NUM 3 #define DQS_INPUT_CAPTURE_FREQ_NUM 6 -//extern u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM]; -//extern u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM]; - -//extern u8 Fixed_DQSA_1_2_Rank_Table[4][2]; -//extern u8 Fixed_DQSA_3_4_Rank_Table[4][2]; -//extern u8 Fixed_DQSB_1_2_Rank_Table[4][2]; -//extern u8 Fixed_DQSB_3_4_Rank_Table[4][2]; #endif /* DRIVINGCLKPHASEDATA_H */ |