diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-17 18:57:12 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-20 21:28:51 +0200 |
| commit | 374c39e3cfbb51927860756d32a77d0afd3752a6 (patch) | |
| tree | a0883ac958a24b7e9341d6860a3fa0b7b5cdf1da /src/northbridge/via/vx800/dram_init.h | |
| parent | 22710a66ac8f01fc4556bb1eaaa50c30352881df (diff) | |
northbridge/via: Add space around operators
Change-Id: I87f8978b8ec6ddc11dd66a77cbb630e057f9831b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16623
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/via/vx800/dram_init.h')
| -rw-r--r-- | src/northbridge/via/vx800/dram_init.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/via/vx800/dram_init.h b/src/northbridge/via/vx800/dram_init.h index 6fa18779d4..e4e143aa0c 100644 --- a/src/northbridge/via/vx800/dram_init.h +++ b/src/northbridge/via/vx800/dram_init.h @@ -75,7 +75,7 @@ #define SPD_SDRAM_COL_ADDR 4 /*Number of column addresses on this assembly */ #define SPD_SDRAM_DIMM_RANKS 5 /*Number of RANKS on this assembly */ #define SPD_SDRAM_MOD_DATA_WIDTH 6 /*Data width of this assembly */ -#define SPD_SDRAM_TCLK_X 9 /*Cycle time at Maximum supported CAS latency (CL=X) */ +#define SPD_SDRAM_TCLK_X 9 /*Cycle time at Maximum supported CAS latency (CL = X) */ #define SPD_SDRAM_TAC_X 10 /*Access time for highest CL */ #define SPD_SDRAM_CONFIG_TYPE 11 /*Non-parity , Parity or ECC */ #define SPD_SDRAM_REFRESH 12 /*Refresh rate/type */ |