diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-17 18:57:12 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-20 21:28:51 +0200 |
commit | 374c39e3cfbb51927860756d32a77d0afd3752a6 (patch) | |
tree | a0883ac958a24b7e9341d6860a3fa0b7b5cdf1da /src/northbridge/via/vx800/dev_init.c | |
parent | 22710a66ac8f01fc4556bb1eaaa50c30352881df (diff) |
northbridge/via: Add space around operators
Change-Id: I87f8978b8ec6ddc11dd66a77cbb630e057f9831b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16623
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/via/vx800/dev_init.c')
-rw-r--r-- | src/northbridge/via/vx800/dev_init.c | 144 |
1 files changed, 72 insertions, 72 deletions
diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c index 819605018e..7cd557a02c 100644 --- a/src/northbridge/via/vx800/dev_init.c +++ b/src/northbridge/via/vx800/dev_init.c @@ -38,13 +38,13 @@ static const u8 DramRegTbl[][3] = { /* Reg AND OR */ {0x50, 0x11, 0xEE}, // DDR default MA7 for DRAM init {0x51, 0x11, 0x60}, // DDR default MA3 for CHB init - {0x52, 0x00, 0x33}, // DDR use BA0=M17, BA1=M18, - {0x53, 0x00, 0x3F}, // DDR BA2=M19 + {0x52, 0x00, 0x33}, // DDR use BA0 = M17, BA1 = M18, + {0x53, 0x00, 0x3F}, // DDR BA2 = M19 - {0x54, 0x00, 0x00}, // default PR0=VR0; PR1=VR1 - {0x55, 0x00, 0x00}, // default PR2=VR2; PR3=VR3 - {0x56, 0x00, 0x00}, // default PR4=VR4; PR5=VR5 - {0x57, 0x00, 0x00}, // default PR4=VR4; PR5=VR5 + {0x54, 0x00, 0x00}, // default PR0 = VR0; PR1 = VR1 + {0x55, 0x00, 0x00}, // default PR2 = VR2; PR3 = VR3 + {0x56, 0x00, 0x00}, // default PR4 = VR4; PR5 = VR5 + {0x57, 0x00, 0x00}, // default PR4 = VR4; PR5 = VR5 {0x60, 0x00, 0x00}, // disable fast turn-around {0x65, 0x00, 0xD9}, // AGP timer = 0XD; Host timer = 8; @@ -317,15 +317,15 @@ Purpose : Initialize DDR2 by standard sequence ===================================================================*/ // DLL: Enable Reset -static const u32 CHA_MRS_DLL_150[2] = { 0x00020200, 0x00000800 }; // with 150 ohm (A17=1, A9=1), (A11=1)(cpu address) -static const u32 CHA_MRS_DLL_75[2] = { 0x00020020, 0x00000800 }; // with 75 ohm (A17=1, A5=1), (A11=1)(cpu address) +static const u32 CHA_MRS_DLL_150[2] = { 0x00020200, 0x00000800 }; // with 150 ohm (A17 = 1, A9 = 1), (A11 = 1)(cpu address) +static const u32 CHA_MRS_DLL_75[2] = { 0x00020020, 0x00000800 }; // with 75 ohm (A17 = 1, A5 = 1), (A11 = 1)(cpu address) // CPU(DRAM) // { DLL: Enable. A17(BA0)=1 and A3(MA0)=0 } // { DLL: reset. A11(MA8)=1 } // -// DDR2 CL=2 CL=3 CL=4 CL=5 CL=6(Burst type=interleave)(WR fine tune in code) -static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 }; // BL=4 ;Use 1X-bandwidth MA table to init DRAM +// DDR2 CL = 2 CL = 3 CL = 4 CL = 5 CL = 6(Burst type = interleave)(WR fine tune in code) +static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 }; // BL = 4 ;Use 1X-bandwidth MA table to init DRAM // MA11 MA10(AP) MA9 #define CHA_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h @@ -334,20 +334,20 @@ static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 #define CHA_MRS_DDR2_TWR5 (1 << 13) + (0 << 20) + (0 << 12) // Value = 002000h #define CHA_MRS_DDR2_TWR6 (1 << 13) + (0 << 20) + (1 << 12) // Value = 003000h -// DDR2 Twr=2 Twr=3 Twr=4 Twr=5 +// DDR2 Twr = 2 Twr = 3 Twr = 4 Twr = 5 static const u32 CHA_DDR2_Twr_table[5] = { CHA_MRS_DDR2_TWR2, CHA_MRS_DDR2_TWR3, CHA_MRS_DDR2_TWR4, CHA_MRS_DDR2_TWR5, CHA_MRS_DDR2_TWR6 }; -#define CHA_OCD_Exit_150ohm 0x20200 // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=1,MA2=0 (DRAM bus address) -// A17=1, A12=A11=A10=0,A9=1 ,A5=0 (CPU address) -#define CHA_OCD_Default_150ohm 0x21E00 // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=1,MA2=0 (DRAM bus address) -// A17=1, A12=A11=A10=1,A9=1 ,A5=0 (CPU address) -#define CHA_OCD_Exit_75ohm 0x20020 // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=0,MA2=1 (DRAM bus address) -// A17=1, A12=A11=A10=0,A9=0 ,A5=1 (CPU address) -#define CHA_OCD_Default_75ohm 0x21C20 // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=0,MA2=1 (DRAM bus address) -// A17=1, A12=A11=A10=1,A9=0 ,A5=1 (CPU address) +#define CHA_OCD_Exit_150ohm 0x20200 // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 1,MA2 = 0 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 0,A9 = 1 ,A5 = 0 (CPU address) +#define CHA_OCD_Default_150ohm 0x21E00 // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 1,MA2 = 0 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 1,A9 = 1 ,A5 = 0 (CPU address) +#define CHA_OCD_Exit_75ohm 0x20020 // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 0,MA2 = 1 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 0,A9 = 0 ,A5 = 1 (CPU address) +#define CHA_OCD_Default_75ohm 0x21C20 // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 0,MA2 = 1 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 1,A9 = 0 ,A5 = 1 (CPU address) void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr) { @@ -527,14 +527,14 @@ Purpose : Initialize DDR2 of CHB by standard sequence Reference : ===================================================================*/ /*// DLL: Enable Reset -static const u32 CHB_MRS_DLL_150[2] = { 0x00020200 | (1 << 20), 0x00000800 }; // with 150 ohm (A17=1, A9=1), (A11=1)(cpu address) -//u32 CHB_MRS_DLL_75[2] = { 0x00020020 | (1 << 20), 0x00000800 }; // with 75 ohm (A17=1, A5=1), (A11=1)(cpu address) +static const u32 CHB_MRS_DLL_150[2] = { 0x00020200 | (1 << 20), 0x00000800 }; // with 150 ohm (A17 = 1, A9 = 1), (A11 = 1)(cpu address) +//u32 CHB_MRS_DLL_75[2] = { 0x00020020 | (1 << 20), 0x00000800 }; // with 75 ohm (A17 = 1, A5 = 1), (A11 = 1)(cpu address) // CPU(DRAM) // { DLL: Enable. A17(BA0)=1 and A3(MA0)=0 } // { DLL: reset. A11(MA8)=1 } // -// DDR2 CL=2 CL=3 CL=4 CL=5 (Burst type=interleave)(WR fine tune in code) -static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // BL=4 ;Use 1X-bandwidth MA table to init DRAM +// DDR2 CL = 2 CL = 3 CL = 4 CL = 5 (Burst type = interleave)(WR fine tune in code) +static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // BL = 4 ;Use 1X-bandwidth MA table to init DRAM // MA11 MA10(AP) MA9 #define CHB_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h @@ -543,17 +543,17 @@ static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // #define CHB_MRS_DDR2_TWR5 (1 << 13) + (0 << 20) + (0 << 12) // Value = 002000h #define CHB_MRS_DDR2_TWR6 (1 << 13) + (0 << 20) + (1 << 12) // Value = 003000h -// DDR2 Twr=2 Twr=3 Twr=4 Twr=5 +// DDR2 Twr = 2 Twr = 3 Twr = 4 Twr = 5 static const u32 CHB_DDR2_Twr_table[5] = { CHB_MRS_DDR2_TWR2, CHB_MRS_DDR2_TWR3, CHB_MRS_DDR2_TWR4, CHB_MRS_DDR2_TWR5, CHB_MRS_DDR2_TWR6 }; -#define CHB_OCD_Exit_150ohm 0x20200 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=1,MA2=0 (DRAM bus address) -// A17=1, A12=A11=A10=0,A9=1 ,A5=0 (CPU address) -#define CHB_OCD_Default_150ohm 0x21E00 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=1,MA2=0 (DRAM bus address) -// A17=1, A12=A11=A10=1,A9=1 ,A5=0 (CPU address) -//#define CHB_OCD_Exit_75ohm 0x20020 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=0,MA2=1 (DRAM bus address) -// A17=1, A12=A11=A10=0,A9=0 ,A5=1 (CPU address) -//#define CHB_OCD_Default_75ohm 0x21C20 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=0,MA2=1 (DRAM bus address) -// A17=1, A12=A11=A10=1,A9=0 ,A5=1 (CPU address) +#define CHB_OCD_Exit_150ohm 0x20200 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 1,MA2 = 0 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 0,A9 = 1 ,A5 = 0 (CPU address) +#define CHB_OCD_Default_150ohm 0x21E00 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 1,MA2 = 0 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 1,A9 = 1 ,A5 = 0 (CPU address) +//#define CHB_OCD_Exit_75ohm 0x20020 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 0,MA2 = 1 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 0,A9 = 0 ,A5 = 1 (CPU address) +//#define CHB_OCD_Default_75ohm 0x21C20 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 0,MA2 = 1 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 1,A9 = 0 ,A5 = 1 (CPU address) void InitDDR2CHB( DRAM_SYS_ATTR *DramAttr ) @@ -568,27 +568,27 @@ void InitDDR2CHB( // step3. //disable bank paging and multi page - Data=pci_read_config8(MEMCTRL, 0x69); + Data = pci_read_config8(MEMCTRL, 0x69); Data &= ~0x03; pci_write_config8(MEMCTRL, 0x69, Data); - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); //step 4. Initialize CHB begin - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data |= 0x40; pci_write_config8(MEMCTRL, 0xd3, Data); //Step 5. NOP command enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x08; pci_write_config8(MEMCTRL, 0xd7, Data); //Step 6. issue a nop cycle,RegD3[7] 0 -> 1 - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; @@ -603,25 +603,25 @@ void InitDDR2CHB( // Step 8. // all banks precharge command enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x10; pci_write_config8(MEMCTRL, 0xd7, Data); //step 9. issue a precharge all cycle,RegD3[7] 0 -> 1 - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); //step10. EMRS enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x18; pci_write_config8(MEMCTRL, 0xd7, Data); - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x08; pci_write_config8(MEMCTRL, 0xd3, Data); @@ -634,25 +634,25 @@ void InitDDR2CHB( Data = (u8)((AccessAddr & 0xff00) >> 8); pci_write_config8(MEMCTRL, 0xda, Data); - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; Data |= (u8)((AccessAddr & 0x30000) >> 15); pci_write_config8(MEMCTRL, 0xd7, Data); //step12. issue EMRS cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); //step13. MSR enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x18; pci_write_config8(MEMCTRL, 0xd7, Data); - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data); @@ -665,13 +665,13 @@ void InitDDR2CHB( Data = (u8)((AccessAddr & 0xff00) >> 8); pci_write_config8(MEMCTRL, 0xda, Data); - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; Data |= (u8)((AccessAddr & 0x30000) >> 15); pci_write_config8(MEMCTRL, 0xd7, Data); //step15. issue MRS cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; @@ -682,21 +682,21 @@ void InitDDR2CHB( pci_write_config8(MEMCTRL, 0xda, Data); //step16. all banks precharge command enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x10; pci_write_config8(MEMCTRL, 0xd7, Data); // step17. issue precharge all cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); //step18. CBR cycle enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x20; pci_write_config8(MEMCTRL, 0xd7, Data); @@ -706,7 +706,7 @@ void InitDDR2CHB( for (Idx = 0; Idx < 8; Idx++) { // issue CBR cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; @@ -716,12 +716,12 @@ void InitDDR2CHB( } //step22. MSR enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x18; pci_write_config8(MEMCTRL, 0xd7, Data); - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data); @@ -730,11 +730,11 @@ void InitDDR2CHB( //the SDRAM parameters.(Burst Length, CAS# Latency , Write recovery etc.) //------------------------------------------------------------- //Burst Length : really offset Rx6c[1] - Data=pci_read_config8(MEMCTRL, 0x6C); + Data = pci_read_config8(MEMCTRL, 0x6C); BL = (Data & 0x02) >> 1; // CL = really offset RX62[2:0] - Data=pci_read_config8(MEMCTRL, 0x62); + Data = pci_read_config8(MEMCTRL, 0x62); CL = Data & 0x03; AccessAddr = (u32)(CHB_DDR2_MRS_table[CL]); @@ -744,7 +744,7 @@ void InitDDR2CHB( } //Write recovery : really offset Rx63[7:5] - Data=pci_read_config8(MEMCTRL, 0x63); + Data = pci_read_config8(MEMCTRL, 0x63); Twr = (Data & 0xE0) >> 5; AccessAddr += CHB_DDR2_Twr_table[Twr]; @@ -758,25 +758,25 @@ void InitDDR2CHB( Data = (u8)((AccessAddr & 0xFF00) >> 8); pci_write_config8(MEMCTRL, 0xda, Data); - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; Data |= (u8)(((AccessAddr & 0x30000)>>16) << 1); pci_write_config8(MEMCTRL, 0xd7, Data); //step 24. issue MRS cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); //step 25. EMRS enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x18; pci_write_config8(MEMCTRL, 0xd7, Data); - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x08; pci_write_config8(MEMCTRL, 0xd3, Data); @@ -790,25 +790,25 @@ void InitDDR2CHB( Data = (u8)((AccessAddr & 0xff00) >> 8); pci_write_config8(MEMCTRL, 0xda, Data); - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; Data |= (u8)((AccessAddr & 0x30000) >> 15); pci_write_config8(MEMCTRL, 0xd7, Data); //step 27. issue EMRS cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); //step 25. EMRS enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x18; pci_write_config8(MEMCTRL, 0xd7, Data); - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x08; pci_write_config8(MEMCTRL, 0xd3, Data); @@ -821,13 +821,13 @@ void InitDDR2CHB( Data = (u8)((AccessAddr & 0xff00) >> 8); pci_write_config8(MEMCTRL, 0xda, Data); - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; Data |= (u8)((AccessAddr & 0x30000) >> 15); pci_write_config8(MEMCTRL, 0xd7, Data); //step 29. issue EMRS cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; @@ -840,29 +840,29 @@ void InitDDR2CHB( Data = 0x00; pci_write_config8(MEMCTRL, 0xda, Data); - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; pci_write_config8(MEMCTRL, 0xd7, Data); //step 30. normal SDRAM Mode - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x00; pci_write_config8(MEMCTRL, 0xd7, Data); - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data); //step 31. exit the initialization mode - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xBF; pci_write_config8(MEMCTRL, 0xd3, Data); //step 32. Enable bank paging and multi page - Data=pci_read_config8(MEMCTRL, 0x69); + Data = pci_read_config8(MEMCTRL, 0x69); Data |= 0x03; pci_write_config8(MEMCTRL, 0x69, Data); } @@ -878,7 +878,7 @@ Output : Void Purpose : Initialize DDR2 of CHC by standard sequence Reference : ===================================================================*/ -// DDR2 CL=2 CL=3 CL=4 CL=5 (Burst type=interleave)(WR fine tune in code) +// DDR2 CL = 2 CL = 3 CL = 4 CL = 5 (Burst type = interleave)(WR fine tune in code) static const u16 CHC_MRS_table[4] = { 0x22B, 0x23B, 0x24B, 0x25B }; // Use 1X-bandwidth MA table to init DRAM void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr) |