Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 16 insertions, 16 deletions

diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c
index 5af7836a93..8fca0eae2c 100644
--- a/src/northbridge/via/vt8601/northbridge.c
+++ b/src/northbridge/via/vt8601/northbridge.c
@@ -18,7 +18,7 @@
  * slower than normal, ethernet drops packets).
  * Apparently these registers govern some sort of bus master behavior.
  */
-static void northbridge_init(device_t dev) 
+static void northbridge_init(device_t dev)
 {
 	printk(BIOS_SPEW, "VT8601 random fixup ...\n");
 	pci_write_config8(dev, 0x70, 0xc0);
@@ -108,16 +108,16 @@ static void pci_domain_set_resources(device_t dev)
 		for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 			unsigned char reg;
 			reg = pci_read_config8(mc_dev, ramregs[i]);
-			/* these are ENDING addresses, not sizes. 
+			/* these are ENDING addresses, not sizes.
 			 * if there is memory in this slot, then reg will be > rambits.
-			 * So we just take the max, that gives us total. 
+			 * So we just take the max, that gives us total.
 			 * We take the highest one to cover for once and future coreboot
 			 * bugs. We warn about bugs.
 			 */
 			if (reg > rambits)
 				rambits = reg;
 			if (reg < rambits)
-				printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", 
+				printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
 					ramregs[i]);
 		}
 		printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
@@ -149,7 +149,7 @@ static struct device_operations pci_domain_ops = {
         .enable_resources = enable_childrens_resources,
         .init             = 0,
         .scan_bus         = pci_domain_scan_bus,
-};  
+};
 
 static void cpu_bus_init(device_t dev)
 {
@@ -182,5 +182,5 @@ static void enable_dev(struct device *dev)
 
 struct chip_operations northbridge_via_vt8601_ops = {
 	CHIP_NAME("VIA VT8601 Northbridge")
-	.enable_dev = enable_dev, 
+	.enable_dev = enable_dev,
 };
diff --git a/src/northbridge/via/vt8601/raminit.c b/src/northbridge/via/vt8601/raminit.c
index cb13ad4e98..2365b8d8fb 100644
--- a/src/northbridge/via/vt8601/raminit.c
+++ b/src/northbridge/via/vt8601/raminit.c
@@ -13,7 +13,7 @@ U.S. Government has rights to use, reproduce, and distribute this
 SOFTWARE.  The public may copy, distribute, prepare derivative works
 and publicly display this SOFTWARE without charge, provided that this
 Notice and any statement of authorship are reproduced on all copies.
-Neither the Government nor the University makes any warranty, express 
+Neither the Government nor the University makes any warranty, express
 or implied, or assumes any liability or responsibility for the use of
 this SOFTWARE.  If SOFTWARE is modified to produce derivative works,
 such modified SOFTWARE should be clearly marked, so as not to confuse
@@ -107,14 +107,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 	pci_write_config8(north, 0x78, 0x01);
 	print_debug_hex8(pci_read_config8(north, 0x78));
 
-	// dram control, see the book. 
+	// dram control, see the book.
 #if DIMM_PC133
 	pci_write_config8(north, 0x68, 0x52);
 #else
 	pci_write_config8(north, 0x68, 0x42);
 #endif
 
-	// dram control, see the book. 
+	// dram control, see the book.
 	pci_write_config8(north, 0x6B, 0x0c);
 
 	// Initial setting, 256MB in each bank, will be rewritten later.
@@ -125,7 +125,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 	pci_write_config8(north, 0x5D, 0x80);
 	pci_write_config8(north, 0x5E, 0xA0);
 	pci_write_config8(north, 0x5F, 0xC0);
-	// It seems we have to take care of these 2 registers as if 
+	// It seems we have to take care of these 2 registers as if
 	// they are bank 6 and 7.
 	pci_write_config8(north, 0x56, 0xC0);
 	pci_write_config8(north, 0x57, 0xC0);
@@ -149,7 +149,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 #endif
 
 	// dram frequency select.
-	// enable 4K pages for 64M dram. 
+	// enable 4K pages for 64M dram.
 #if DIMM_PC133
 	pci_write_config8(north, 0x69, 0x3c);
 #else
@@ -181,8 +181,8 @@ static unsigned long spd_module_size(unsigned char slot)
 	/* unsigned int module = ((0x50 + slot) << 1) + 1; */
 	unsigned int module = 0x50 + slot;
 
-	/* is the module there? if byte 2 is not 4, then we'll assume it 
-	 * is useless. 
+	/* is the module there? if byte 2 is not 4, then we'll assume it
+	 * is useless.
 	 */
 	print_info("Slot ");
 	print_info_hex8(slot);
@@ -292,7 +292,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	pci_write_config8(north, 0x6C, 0x01);
 	print_debug("NOP\n");
 	/* wait 200us */
-	// You need to do the memory reference. That causes the nop cycle. 
+	// You need to do the memory reference. That causes the nop cycle.
 	dimms_read(0);
 	udelay(400);
 	print_debug("PRECHARGE\n");
@@ -340,7 +340,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	dimms_read(0);
 	udelay(200);
 	print_debug("set ref. rate\n");
-	// Set the refresh rate. 
+	// Set the refresh rate.
 #if DIMM_PC133
 	pci_write_config8(north, 0x6A, 0x86);
 #else
@@ -370,7 +370,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 		/* Set the MA map type.
 		 *
-		 * 0xa should be another option, but when 
+		 * 0xa should be another option, but when
 		 * it would be used is unknown.
 		 */