northbridge: Drop print_ implementation from non-romcc boards

Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the northbridge code to use printk() on all non-ROMCC
boards.

Change-Id: I4a36cd965c58aae65d74ce1e697dc0d0f58f47a1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7856
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)

2 files changed, 29 insertions, 45 deletions

diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c
index 7c77bff350..39e1753059 100644
--- a/src/northbridge/via/cx700/early_smbus.c
+++ b/src/northbridge/via/cx700/early_smbus.c
@@ -46,15 +46,6 @@
 
 #define SMBUS_DELAY()		outb(0x80, 0x80)
 
-/* Debugging macros. */
-#if CONFIG_DEBUG_SMBUS
-#define PRINT_DEBUG(x)		print_debug(x)
-#define PRINT_DEBUG_HEX16(x)	print_debug_hex16(x)
-#else
-#define PRINT_DEBUG(x)
-#define PRINT_DEBUG_HEX16(x)
-#endif
-
 /* Internal functions */
 #if CONFIG_DEBUG_SMBUS
 static void smbus_print_error(unsigned char host_status_register, int loops)
@@ -63,28 +54,26 @@ static void smbus_print_error(unsigned char host_status_register, int loops)
 	if (host_status_register == 0x00 || host_status_register == 0x40 ||
 	    host_status_register == 0x42)
 		return;
-	print_err("SMBus Error: ");
-	print_err_hex8(host_status_register);
+	printk(BIOS_ERR, "SMBus Error: %02x\n", host_status_register);
 
-	print_err("\n");
 	if (loops >= SMBUS_TIMEOUT) {
-		print_err("SMBus Timout\n");
+		printk(BIOS_ERR, "SMBus Timout\n");
 	}
 	if (host_status_register & (1 << 4)) {
-		print_err("Interrup/SMI# was Failed Bus Transaction\n");
+		printk(BIOS_ERR, "Interrup/SMI# was Failed Bus Transaction\n");
 	}
 	if (host_status_register & (1 << 3)) {
-		print_err("Bus Error\n");
+		printk(BIOS_ERR, "Bus Error\n");
 	}
 	if (host_status_register & (1 << 2)) {
-		print_err("Device Error\n");
+		printk(BIOS_ERR, "Device Error\n");
 	}
 	if (host_status_register & (1 << 1)) {
 		/* This isn't a real error... */
-		print_debug("Interrupt/SMI# was Successful Completion\n");
+		printk(BIOS_DEBUG, "Interrupt/SMI# was Successful Completion\n");
 	}
 	if (host_status_register & (1 << 0)) {
-		print_err("Host Busy\n");
+		printk(BIOS_ERR, "Host Busy\n");
 	}
 }
 #endif
@@ -239,9 +228,7 @@ static void dump_spd_data(const struct mem_controller *ctrl)
 	unsigned int val;
 
 	for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
-		print_debug("SPD Data for DIMM ");
-		print_debug_hex8(dimm);
-		print_debug("\n");
+		printk(BIOS_DEBUG, "SPD Data for DIMM %02x\n", dimm);
 
 		val = get_spd_data(ctrl, dimm, 0);
 		if (val == 0xff) {
@@ -249,15 +236,12 @@ static void dump_spd_data(const struct mem_controller *ctrl)
 		} else if (val == 0x80) {
 			regs = 128;
 		} else {
-			print_debug("No DIMM present\n");
+			printk(BIOS_DEBUG, "No DIMM present\n");
 			regs = 0;
 		}
 		for (offset = 0; offset < regs; offset++) {
-			print_debug("  Offset ");
-			print_debug_hex8(offset);
-			print_debug(" = 0x");
-			print_debug_hex8(get_spd_data(ctrl, dimm, offset));
-			print_debug("\n");
+			printk(BIOS_DEBUG, "  Offset %02x = 0x%02x\n",
+				offset, get_spd_data(ctrl, dimm, offset));
 		}
 	}
 }
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index a2e6dad01e..32be1ea4cd 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -972,7 +972,7 @@ static void step_20_21(const struct mem_controller *ctrl)
 		read32(0x102020);
 
 	/* Step 21. Normal operation */
-	print_spew("RAM Enable 5: Normal operation\n");
+	printk(BIOS_SPEW, "RAM Enable 5: Normal operation\n");
 	do_ram_command(ctrl, RAM_COMMAND_NORMAL);
 	udelay(3);
 }
@@ -988,58 +988,58 @@ static void step_2_19(const struct mem_controller *ctrl)
 	pci_write_config8(MEMCTRL, 0x69, val);
 
 	/* Step 3 Apply NOP. */
-	print_spew("RAM Enable 1: Apply NOP\n");
+	printk(BIOS_SPEW, "RAM Enable 1: Apply NOP\n");
 	do_ram_command(ctrl, RAM_COMMAND_NOP);
 
 	udelay(15);
 
 	// Step 4
-	print_spew("SEND: ");
+	printk(BIOS_SPEW, "SEND: ");
 	read32(0);
-	print_spew("OK\n");
+	printk(BIOS_SPEW, "OK\n");
 
 	// Step 5
 	udelay(400);
 
 	/* 6. Precharge all. Wait tRP. */
-	print_spew("RAM Enable 2: Precharge all\n");
+	printk(BIOS_SPEW, "RAM Enable 2: Precharge all\n");
 	do_ram_command(ctrl, RAM_COMMAND_PRECHARGE);
 
 	// Step 7
-	print_spew("SEND: ");
+	printk(BIOS_SPEW, "SEND: ");
 	read32(0);
-	print_spew("OK\n");
+	printk(BIOS_SPEW, "OK\n");
 
 	/* Step 8. Mode register set. */
-	print_spew("RAM Enable 4: Mode register set\n");
+	printk(BIOS_SPEW, "RAM Enable 4: Mode register set\n");
 	do_ram_command(ctrl, RAM_COMMAND_MRS);	//enable dll
 
 	// Step 9
-	print_spew("SEND: ");
+	printk(BIOS_SPEW, "SEND: ");
 
 	val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
 	if (val & DDR2_ODT_150ohm)
 		read32(0x102200);	//DDR2_ODT_150ohm
 	else
 		read32(0x102020);
-	print_spew("OK\n");
+	printk(BIOS_SPEW, "OK\n");
 
 	// Step 10
-	print_spew("SEND: ");
+	printk(BIOS_SPEW, "SEND: ");
 	read32(0x800);
-	print_spew("OK\n");
+	printk(BIOS_SPEW, "OK\n");
 
 	/* Step 11. Precharge all. Wait tRP. */
-	print_spew("RAM Enable 2: Precharge all\n");
+	printk(BIOS_SPEW, "RAM Enable 2: Precharge all\n");
 	do_ram_command(ctrl, RAM_COMMAND_PRECHARGE);
 
 	// Step 12
-	print_spew("SEND: ");
+	printk(BIOS_SPEW, "SEND: ");
 	read32(0x0);
-	print_spew("OK\n");
+	printk(BIOS_SPEW, "OK\n");
 
 	/* Step 13. Perform 8 refresh cycles. Wait tRC each time. */
-	print_spew("RAM Enable 3: CBR\n");
+	printk(BIOS_SPEW, "RAM Enable 3: CBR\n");
 	do_ram_command(ctrl, RAM_COMMAND_CBR);
 
 	/* JEDEC says only twice, do 8 times for posterity */
@@ -1047,14 +1047,14 @@ static void step_2_19(const struct mem_controller *ctrl)
 	for (i = 0; i < 8; i++) {
 		// Step 14
 		read32(0);
-		print_spew(".");
+		printk(BIOS_SPEW, ".");
 
 		// Step 15
 		udelay(100);
 	}
 
 	/* Step 17. Mode register set. Wait 200us. */
-	print_spew("\nRAM Enable 4: Mode register set\n");
+	printk(BIOS_SPEW, "\nRAM Enable 4: Mode register set\n");
 
 	//safe value for now, BL=8, WR=4, CAS=4
 	do_ram_command(ctrl, RAM_COMMAND_MRS);