diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2009-04-17 08:37:18 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2009-04-17 08:37:18 +0000 |
commit | aeba92ab5b0afd1464d6b1a275b5f5b00b351b32 (patch) | |
tree | 225fbff67fc05e70507ac6ef7b3af32f00bac6f8 /src/northbridge/via/cx700/cx700_early_serial.c | |
parent | 56c51bd120a935e64cfd96d8ad71c9d1f7aab323 (diff) |
Add VIA CX700 support, plus VIA vt8454c reference board support.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/via/cx700/cx700_early_serial.c')
-rw-r--r-- | src/northbridge/via/cx700/cx700_early_serial.c | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/src/northbridge/via/cx700/cx700_early_serial.c b/src/northbridge/via/cx700/cx700_early_serial.c new file mode 100644 index 0000000000..a0d7301e20 --- /dev/null +++ b/src/northbridge/via/cx700/cx700_early_serial.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Enable the serial devices on the VIA CX700 + */ + +#include <arch/romcc_io.h> + +static void cx700_writepnpaddr(u8 val) +{ + outb(val, 0x2e); + outb(val, 0xeb); +} + +static void cx700_writepnpdata(u8 val) +{ + outb(val, 0x2f); + outb(val, 0xeb); +} + +static void cx700_writesiobyte(u16 reg, u8 val) +{ + outb(val, reg); +} + +static void cx700_writesioword(u16 reg, u16 val) +{ + outw(val, reg); +} + +static void enable_cx700_serial(void) +{ + outb(6, 0x80); + + // WTH? + outb(0x03, 0x22); + + // Set UART1 I/O Base Address + pci_write_config8(PCI_DEV(0, 17, 0), 0xb4, 0x7e); + + // UART1 Enable + pci_write_config8(PCI_DEV(0, 17, 0), 0xb0, 0x10); + + // turn on pnp + cx700_writepnpaddr(0x87); + cx700_writepnpaddr(0x87); + // now go ahead and set up com1. + // set address + cx700_writepnpaddr(0x7); + cx700_writepnpdata(0x2); + // enable serial out + cx700_writepnpaddr(0x30); + cx700_writepnpdata(0x1); + // serial port 1 base address (FEh) + cx700_writepnpaddr(0x60); + cx700_writepnpdata(0xfe); + // serial port 1 IRQ (04h) + cx700_writepnpaddr(0x70); + cx700_writepnpdata(0x4); + // serial port 1 control + cx700_writepnpaddr(0xf0); + cx700_writepnpdata(0x2); + // turn of pnp + cx700_writepnpaddr(0xaa); + + // XXX This part should be fully taken care of by + // src/pc80/serial.c:uart_init + + // set up reg to set baud rate. + cx700_writesiobyte(0x3fb, 0x80); + // Set 115 kb + cx700_writesioword(0x3f8, 1); + // Set 9.6 kb + // cx700_writesioword(0x3f8, 12) + // now set no parity, one stop, 8 bits + cx700_writesiobyte(0x3fb, 3); + // now turn on RTS, DRT + cx700_writesiobyte(0x3fc, 3); + // Enable interrupts + cx700_writesiobyte(0x3f9, 0xf); + // should be done. Dump a char for fun. + cx700_writesiobyte(0x3f8, 48); + + outb(7, 0x80); +} |