diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-17 18:57:12 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-20 21:28:51 +0200 |
| commit | 374c39e3cfbb51927860756d32a77d0afd3752a6 (patch) | |
| tree | a0883ac958a24b7e9341d6860a3fa0b7b5cdf1da /src/northbridge/via/cn700 | |
| parent | 22710a66ac8f01fc4556bb1eaaa50c30352881df (diff) | |
northbridge/via: Add space around operators
Change-Id: I87f8978b8ec6ddc11dd66a77cbb630e057f9831b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16623
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/via/cn700')
| -rw-r--r-- | src/northbridge/via/cn700/raminit.c | 8 | ||||
| -rw-r--r-- | src/northbridge/via/cn700/vga.c | 22 |
2 files changed, 15 insertions, 15 deletions
diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c index f85f68e619..e4384ce697 100644 --- a/src/northbridge/via/cn700/raminit.c +++ b/src/northbridge/via/cn700/raminit.c @@ -258,9 +258,9 @@ static void sdram_set_registers(const struct mem_controller *ctrl) { u8 reg; - /* Set WR=5 */ + /* Set WR = 5 */ pci_write_config8(ctrl->d0f3, 0x61, 0xe0); - /* Set CAS=4 */ + /* Set CAS = 4 */ pci_write_config8(ctrl->d0f3, 0x62, 0xfa); /* DRAM timing-3 */ pci_write_config8(ctrl->d0f3, 0x63, 0xca); @@ -283,7 +283,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) pci_write_config8(ctrl->d0f3, 0x52, 0x33); pci_write_config8(ctrl->d0f3, 0x53, 0x3f); - /* Set to DDR2 SDRAM, BL=8 (0xc8, 0xc0 for bl=4) */ + /* Set to DDR2 SDRAM, BL = 8 (0xc8, 0xc0 for bl = 4) */ pci_write_config8(ctrl->d0f3, 0x6c, 0xc8); /* DRAM Bus Turn-Around Setting */ @@ -426,7 +426,7 @@ static void sdram_enable(device_t dev, u8 *rank_address) /* 6. Mode register set. */ PRINT_DEBUG_MEM("RAM Enable 6: Mode register set\n"); - /* Safe value for now, BL=8, WR=5, CAS=4 */ + /* Safe value for now, BL = 8, WR = 5, CAS = 4 */ /* * (E)MRS values are from the BPG. No direct explanation is given, but * they should somehow conform to the JEDEC DDR2 SDRAM Specification diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c index 10b7f65a5d..4925f2b44e 100644 --- a/src/northbridge/via/cn700/vga.c +++ b/src/northbridge/via/cn700/vga.c @@ -35,16 +35,16 @@ static int via_cn700_int15_handler(void) { - int res=0; + int res = 0; printk(BIOS_DEBUG, "via_cn700_int15_handler\n"); switch(X86_EAX & 0xffff) { case 0x5f19: break; case 0x5f18: - X86_EAX=0x5f; - X86_EBX=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory - X86_ECX=0x060; - res=1; + X86_EAX = 0x5f; + X86_EBX = 0x545; // MCLK = 133, 32M frame buffer, 256 M main memory + X86_ECX = 0x060; + res = 1; break; case 0x5f00: X86_EAX = 0x8600; @@ -55,14 +55,14 @@ static int via_cn700_int15_handler(void) res = 1; break; case 0x5f02: - X86_EAX=0x5f; - X86_EBX= (X86_EBX & 0xffff0000) | 2; - X86_ECX= (X86_ECX & 0xffff0000) | 0x401; // PAL + crt only - X86_EDX= (X86_EDX & 0xffff0000) | 0; // TV Layout - default - res=1; + X86_EAX = 0x5f; + X86_EBX = (X86_EBX & 0xffff0000) | 2; + X86_ECX = (X86_ECX & 0xffff0000) | 0x401; // PAL + crt only + X86_EDX = (X86_EDX & 0xffff0000) | 0; // TV Layout - default + res = 1; break; case 0x5f0f: - X86_EAX=0x860f; + X86_EAX = 0x860f; break; default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", |