diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-27 06:56:47 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-27 06:56:47 +0000 |
| commit | 14e22779625de673569c7b950ecc2753fb915b31 (patch) | |
| tree | 14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /src/northbridge/via/cn700 | |
| parent | 0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff) | |
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/via/cn700')
| -rw-r--r-- | src/northbridge/via/cn700/raminit.c | 6 | ||||
| -rw-r--r-- | src/northbridge/via/cn700/vga.c | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c index 63dab5b3e0..20b0afeb6e 100644 --- a/src/northbridge/via/cn700/raminit.c +++ b/src/northbridge/via/cn700/raminit.c @@ -51,7 +51,7 @@ static void do_ram_command(device_t dev, u8 command) } /** - * Configure the bus between the CPU and the northbridge. This might be able to + * Configure the bus between the CPU and the northbridge. This might be able to * be moved to post-ram code in the future. For the most part, these registers * should not be messed around with. These are too complex to explain short of * copying the datasheets into the comments, but most of these values are from @@ -244,7 +244,7 @@ static void sdram_set_size(const struct mem_controller *ctrl) } /** - * Set up various RAM and other control registers statically. Some of these may + * Set up various RAM and other control registers statically. Some of these may * not be needed, other should be done with SPD info, but that's a project for * the future. */ @@ -422,7 +422,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address) PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n"); /* Safe value for now, BL=8, WR=5, CAS=4 */ /* - * (E)MRS values are from the BPG. No direct explanation is given, but + * (E)MRS values are from the BPG. No direct explanation is given, but * they should somehow conform to the JEDEC DDR2 SDRAM Specification * (JESD79-2C). */ diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c index 69f188b01e..33d1fe0071 100644 --- a/src/northbridge/via/cn700/vga.c +++ b/src/northbridge/via/cn700/vga.c @@ -62,7 +62,7 @@ static int via_cn700_int15_handler(struct eregs *regs) case 0x5f02: regs->eax=0x5f; regs->ebx= (regs->ebx & 0xffff0000) | 2; - regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only + regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default res=0; break; @@ -70,7 +70,7 @@ static int via_cn700_int15_handler(struct eregs *regs) regs->eax=0x860f; break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", regs->eax & 0xffff); break; } |