diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2014-07-27 19:37:31 +0200 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-07-29 04:40:27 +0200 |
| commit | 0f92f630556b4bf2e4c0696cae4c2f8e97eda334 (patch) | |
| tree | b97ad7a89a101c4770774035db5e4693043be928 /src/northbridge/via/cn400 | |
| parent | 081651b6677c64a5f2861d831822b5f8f3517c21 (diff) | |
Uniformly spell frequency unit symbol as Hz
Change-Id: I1eb8d5bd79322ff3654a6ad66278a57d46a818c1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/6384
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/northbridge/via/cn400')
| -rw-r--r-- | src/northbridge/via/cn400/raminit.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c index 23a6209458..d15a6338e0 100644 --- a/src/northbridge/via/cn400/raminit.c +++ b/src/northbridge/via/cn400/raminit.c @@ -333,7 +333,7 @@ static void ddr_ram_setup(void) } } if( b & 0x04 ){ // DDR mandatory CAS 2 - if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2 + if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max MHz at CAS 2 //print_debug("\nWe can do CAS 2"); c = 0x10; } @@ -342,7 +342,7 @@ static void ddr_ram_setup(void) //print_debug("\nStarting at CAS 2.5"); c = 0x20; // assume CAS 2.5 if( b & 0x04){ // Should always happen - if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2 + if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max MHz at CAS 2 //print_debug("\nWe can do CAS 2"); c = 0x10; } |