Ron,

Attached is the third revision of the CN400/EPIA-N(L) patch for CB V2.

Patch should work against r4381 (or later ?)

This version now boots all of the way through to attempting to launch a
payload (I'm trying FILO right now), where it falls over with exception
6 (invalid opcode)

The coreboot_table issue seems to have been automagically resolved by
the latest core files.

It may still be that the reason for the payload not starting is down to
some issue with the tables initialising, I'll look closer at that.

Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>

Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 31 insertions, 0 deletions

diff --git a/src/northbridge/via/cn400/raminit.h b/src/northbridge/via/cn400/raminit.h
new file mode 100644
index 0000000000..64f8db4fb4
--- /dev/null
+++ b/src/northbridge/via/cn400/raminit.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef RAMINIT_H
+#define RAMINIT_H
+
+#define DIMM_SOCKETS 1		/* Only one works, for now. */
+
+struct mem_controller {
+	device_t d0f0, d0f2, d0f3, d0f4, d0f7, d1f0;
+	u8 channel0[DIMM_SOCKETS];
+};
+
+#endif