diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-15 13:19:07 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-18 10:14:56 +0000 |
| commit | ff254ea60bd489c87f566f1f71585d546a8e844a (patch) | |
| tree | df0f8278e3d68b172c2038491345a2499ca96e61 /src/northbridge/intel | |
| parent | 7a940dfb22461da543cc6f68c5db237c930cebf7 (diff) | |
nb/intel/pineview: Drop unused `GPIO32` macro
It's not used, and GPIO registers are on the southbridge.
Change-Id: I0b7b6edc22d461007f24618eca42091439a53d3c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45423
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/pineview/pineview.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 914c3a3575..f2ae1c44c1 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -27,8 +27,6 @@ #define GTTADR 0x1c #define BSM 0x5c -#define GPIO32(x) *((volatile u32 *)(DEFAULT_GPIOBASE + x)) - /* * MCHBAR */ |