diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 11:26:35 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-10 07:29:54 +0000 |
| commit | e88f705946a1f8b18ff421c654a568581b1e969e (patch) | |
| tree | 9b476bdbd17d70e47f228ab8459db50df0cadf14 /src/northbridge/intel | |
| parent | 24b1d8af060fa0aabb8b127716ba5c5ed87f5edf (diff) | |
nb/intel/x4x: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.
Change-Id: I33c17f56eac0277a12b32af777e2e1ceb086685f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/x4x/Kconfig | 9 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/acpi/x4x.asl | 7 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/early_init.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/memmap.h | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 13 |
5 files changed, 17 insertions, 21 deletions
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 711340d376..99f6d794fd 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -37,4 +37,13 @@ config MAX_CPUS int default 4 +config FIXED_MCHBAR_MMIO_BASE + default 0xfed14000 + +config FIXED_DMIBAR_MMIO_BASE + default 0xfed18000 + +config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + endif diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 9eed44ecff..8ef0ca4eca 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include "hostbridge.asl" -#include "../memmap.h" /* PCI Device Resource Consumption */ Device (PDRC) @@ -11,9 +10,9 @@ Device (PDRC) Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 279a38fcd6..ea41e76dce 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -15,13 +15,13 @@ void x4x_early_init(void) { /* Setup MCHBAR. */ - pci_write_config32(HOST_BRIDGE, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, D0F0_MCHBAR_LO, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); /* Setup DMIBAR. */ - pci_write_config32(HOST_BRIDGE, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, D0F0_DMIBAR_LO, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); /* Setup EPBAR. */ - pci_write_config32(HOST_BRIDGE, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); + pci_write_config32(HOST_BRIDGE, D0F0_EPBAR_LO, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); /* Setup HECIBAR */ pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR); diff --git a/src/northbridge/intel/x4x/memmap.h b/src/northbridge/intel/x4x/memmap.h index e4aafffbf6..030b9e2665 100644 --- a/src/northbridge/intel/x4x/memmap.h +++ b/src/northbridge/intel/x4x/memmap.h @@ -3,9 +3,6 @@ #ifndef X4X_MEMMAP_H #define X4X_MEMMAP_H -#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_HECIBAR 0xfed10000 #define TPM_BASE_ADDRESS 0xfed40000 diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 33f7a4c134..b5842eef0d 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -44,9 +44,8 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#include <northbridge/intel/common/fixed_bars.h> + #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) @@ -93,10 +92,6 @@ * DMIBAR */ -#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) - #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ @@ -138,10 +133,6 @@ * EPBAR */ -#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) - #define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCTL 0x00c /* 32bit */ |