diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-19 12:53:36 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-22 22:13:28 +0000 |
| commit | 9fbb1b096ff64e83a822d165fb732f22a2ec6e79 (patch) | |
| tree | 114937a1f3b5d9a1be3790a43483b329e2fd9ae5 /src/northbridge/intel | |
| parent | 09fc4b90ebfdb81914f6b89b676db101a417414a (diff) | |
nb/intel/sandybridge: Only use write Vref if supported
Only some Ivy Bridge SKUs support write Vref control.
Change-Id: I4e606c69c6758d909946da43c3d243e3af8833cf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 7 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/registers/host_bridge.h | 1 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index d533ca8a30..01dfcc4a7e 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2459,6 +2459,13 @@ int discover_timC_write(ramctr_timing *ctrl) int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int channel, slotrank, lane; + /* Changing the write Vref is only supported on some Ivy Bridge SKUs */ + if (!IS_IVY_CPU(ctrl->cpu)) + return 0; + + if (!(pci_read_config32(HOST_BRIDGE, CAPID0_A) & CAPID_WRTVREF)) + return 0; + FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { lower[channel][slotrank][lane] = 0; upper[channel][slotrank][lane] = MAX_TIMC; diff --git a/src/northbridge/intel/sandybridge/registers/host_bridge.h b/src/northbridge/intel/sandybridge/registers/host_bridge.h index 4814b94b6f..95998714c8 100644 --- a/src/northbridge/intel/sandybridge/registers/host_bridge.h +++ b/src/northbridge/intel/sandybridge/registers/host_bridge.h @@ -52,6 +52,7 @@ #define CAPID_ECCDIS (1 << 25) #define CAPID_DDPCD (1 << 14) #define CAPID_PDCD (1 << 12) +#define CAPID_WRTVREF (1 << 1) #define CAPID_DDRSZ(x) (((x) >> 19) & 0x3) #define CAPID0_B 0xe8 /* Capabilities Register B */ |