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authorElyes Haouas <ehaouas@noos.fr>2023-06-24 10:16:28 +0200
committerMartin L Roth <gaumless@gmail.com>2023-06-28 19:32:22 +0000
commit9b3e5cdc20977890da65dbd53b88147876440b65 (patch)
tree4f3eb640f8a85d5f036052786f4d7ae3e10be2ac /src/northbridge/intel
parentddbe8322a508bbfa9aaf1cf5a2b83c8d2eb5f1ef (diff)
nb/intel/pineview: Drop unused attributes from sysinfo struct
Change-Id: Iab582458a7dd87e10bf14fd34f15c592b600f706 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/pineview/raminit.h10
1 files changed, 0 insertions, 10 deletions
diff --git a/src/northbridge/intel/pineview/raminit.h b/src/northbridge/intel/pineview/raminit.h
index 4a0547b305..fb3397610a 100644
--- a/src/northbridge/intel/pineview/raminit.h
+++ b/src/northbridge/intel/pineview/raminit.h
@@ -95,19 +95,10 @@ struct sysinfo {
u16 mediumphase;
u16 readptrdelay;
- int txt_enabled;
- int cores;
int boot_path;
- int max_ddr2_mhz;
- int max_ddr3_mt;
- int max_fsb_mhz;
- int max_render_mhz;
- int enable_igd;
- int enable_peg;
u16 ggc;
int dimm_config[2];
- int dimms_per_ch;
int spd_type;
int channel_capacity[2];
struct timings selected_timings;
@@ -117,7 +108,6 @@ struct sysinfo {
u8 nodll;
u8 async;
u8 dt0mode;
- u8 mvco4x; /* 0 (8x) or 1 (4x) */
};
void sdram_initialize(int boot_path, const u8 *sdram_addresses);