diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2024-04-16 17:33:58 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-04-18 11:03:40 +0000 |
| commit | 8b5aacca3f2c16fc4153887a6289e2c3eca9d10d (patch) | |
| tree | a6708fcf942b047d832b2513e438c331d8e3d1c0 /src/northbridge/intel | |
| parent | 7d3e161d70d1265c26baf59546dfcaac4ac2fb4c (diff) | |
nb/intel/gm45: Call `mb_post_raminit_setup()` later
The only implementations of `mb_post_raminit_setup()` in the tree are
found in Lenovo ThinkPads. These boards use this function to toggle a
SMBus mux, which makes the DIMM SPDs inaccessible. Given that the SPD
data is needed in `setup_sdram_meminfo()` and that there are no other
side-effects, simply move the call to `mb_post_raminit_setup()` after
the call to `setup_sdram_meminfo()`.
TEST=Verify SMBIOS Type 17 information for lenovo/x200 is correct.
Change-Id: I46abffa48e7e0848f9346ce9c6498860e4ece2da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/gm45/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 9ed3c00154..bc17618b03 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -74,8 +74,6 @@ void mainboard_romstage_entry(void) raminit(&sysinfo, s3resume); - mb_post_raminit_setup(); - /* Disable D4F0 (unknown signal controller). */ pci_and_config32(MCH_DEV, D0F0_DEVEN, ~0x4000); @@ -93,6 +91,8 @@ void mainboard_romstage_entry(void) setup_sdram_meminfo(&sysinfo); + mb_post_raminit_setup(); + romstage_handoff_init(cbmem_initted && s3resume); printk(BIOS_SPEW, "exit main()\n"); |