diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-17 14:16:03 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-06-02 21:56:06 +0000 |
| commit | 4c0e277e4ea358f7a36a75b503def54578fcd536 (patch) | |
| tree | ca70cb5959a95d0cf5302c5ef1bbec248fe6f50f /src/northbridge/intel | |
| parent | 717b6e3151b6ea42aaa4b1ab2a708e143d098878 (diff) | |
intel/e7505: Assume AGP slot disabled
Reducing two AGP aperture windows from default 256 MiB to
chipset minimum 4 MiB releases 504 MiB of unused MMIO space.
Thus we can decrease MMIO space reserve from 1024 MiB to 512 MiB.
Supported CPUs are 32-bit with PAE, so there is a little reason
to avoid overlarge MMIO region.
Change-Id: I34818e1ca36058309c7c5c295992ba6dda154acc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/e7505/e7505.h | 5 | ||||
| -rw-r--r-- | src/northbridge/intel/e7505/raminit.c | 20 |
2 files changed, 21 insertions, 4 deletions
diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index 9c9171d2bd..5ceeacceaf 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -42,6 +42,7 @@ #define DRC 0x7C /* DRAM Controller Mode register, 32 bit */ #define DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */ #define CKDIS 0x8C /* Clock disable register, 8 bit */ +#define APSIZE 0xB4 #define TOLM 0xC4 /* Top of Low Memory register, 16 bit */ #define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */ #define REMAPLIMIT 0xC8 /* Remap Limit Address register, 16 bit */ @@ -82,4 +83,8 @@ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ +/************ D1:F0 ************/ + +#define APSIZE1 0x74 + #endif /* NORTHBRIDGE_INTEL_E7505_E7505_H */ diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 7464a722fa..1cbed5ab3d 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -68,9 +68,10 @@ Definitions: #define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4) #define SPD_ERROR "Error reading SPD info\n" -#define MCHDEV PCI_DEV(0,0,0) -#define RASDEV PCI_DEV(0,0,1) -#define D060DEV PCI_DEV(0,6,0) +#define MCHDEV PCI_DEV(0, 0, 0) +#define RASDEV PCI_DEV(0, 0, 1) +#define AGPDEV PCI_DEV(0, 1, 0) +#define D060DEV PCI_DEV(0, 6, 0) // NOTE: This used to be 0x100000. // That doesn't work on systems where A20M# is asserted, because @@ -853,6 +854,9 @@ static void configure_e7501_ram_addresses(const struct mem_controller uint64_t tolm, tom; uint16_t reg; + /* FIXME: Is there standard presence detect bit somewhere. */ + const int agp_slot_disabled = 1; + /* Start with disabled remap range. */ uint16_t remapbase_r = 0x3ff; uint16_t remaplimit_r = 0; @@ -888,7 +892,15 @@ static void configure_e7501_ram_addresses(const struct mem_controller tom = total_dram_64M_multiple * 64ULL * MiB; /* Reserve MMIO space. */ - tolm = 4ULL * GiB - 1 * GiB; + tolm = 4ULL * GiB - 512 * MiB; + if (agp_slot_disabled) { + /* Reduce apertures to 2 x 4 MiB. */ + pci_write_config8(MCHDEV, APSIZE, 0x3F); + pci_write_config16(AGPDEV, APSIZE1, 0x3F); + } else { + /* Add MMIO reserve for 2 x 256 MiB apertures. */ + tolm -= 512 * MiB; + } tolm = MIN(tolm, tom); /* The PCI memory hole overlaps memory setup the remap window. */ |