diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-02-10 22:21:39 -0600 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-16 21:02:30 +0100 |
| commit | 033bb4bc8d620288ed82fe982a32f567060499b6 (patch) | |
| tree | bba24a07d463455825363b54894da14a6ba07025 /src/northbridge/intel | |
| parent | 4f731f2eabc9ef2c381b71515a3b2ff203c8653e (diff) | |
acpi: Generate valid ACPI processor objects
The existing code generated invalid ACPI processor objects
if the core number was greater than 9. The first invalid
object instance was autocorrected by Linux, but subsequent
instances conflicted with each other, leading to a failure
to boot if more than 10 CPU cores were installed.
The modified code will function with up to 99 cores.
Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8422
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/northbridge/intel')
4 files changed, 12 insertions, 12 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl index e569cf30b2..e82758c494 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl @@ -147,16 +147,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index bb8e95ef0b..9bc5549041 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -157,16 +157,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl index 79736bcafd..d210a95064 100644 --- a/src/northbridge/intel/nehalem/acpi/hostbridge.asl +++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl @@ -109,16 +109,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 427927182d..26f7514646 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -147,16 +147,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } |