nb/intel: Add missing <types.h>

Add needed but missing <types.h>.

Change-Id: I801be1ca8da4b1641941d5571d2aa298470f407b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50578
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

6 files changed, 8 insertions, 5 deletions

diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 4fe3998bee..28edb381a1 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -3,7 +3,6 @@
 // Use simple device model for this file even in ramstage
 #define __SIMPLE_DEVICE__
 
-#include <stdint.h>
 #include <arch/romstage.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
@@ -13,6 +12,8 @@
 #include <cbmem.h>
 #include <program_loading.h>
 #include <cpu/intel/smm_reloc.h>
+#include <types.h>
+
 #include "gm45.h"
 
 /*
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 501caf17f1..c59dce792f 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -3,7 +3,6 @@
 #include <commonlib/helpers.h>
 #include <console/console.h>
 #include <acpi/acpi.h>
-#include <stdint.h>
 #include <delay.h>
 #include <cpu/intel/haswell/haswell.h>
 #include <device/device.h>
@@ -14,6 +13,7 @@
 #include <boot/tables.h>
 #include <security/intel/txt/txt_register.h>
 #include <southbridge/intel/lynxpoint/pch.h>
+#include <types.h>
 
 #include "chip.h"
 #include "haswell.h"
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 9617ffb59d..96e6a2aeff 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -16,6 +16,8 @@
 #include <spd.h>
 #include <security/vboot/vboot_common.h>
 #include <commonlib/region.h>
+#include <types.h>
+
 #include "raminit.h"
 #include "pei_data.h"
 #include "haswell.h"
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index c92e4662d6..1dea21c6d6 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -12,7 +12,7 @@
 #include <cpu/x86/smm.h>
 #include <program_loading.h>
 #include <cpu/intel/smm_reloc.h>
-#include <stdint.h>
+#include <types.h>
 
 /* Decodes TSEG region size to bytes. */
 u32 decode_tseg_size(const u8 esmramc)
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index 58342795b2..c02cf35712 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -13,7 +13,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <cpu/intel/smm_reloc.h>
-#include <stdint.h>
+#include <types.h>
 
 /** Decodes used Graphics Mode Select (GMS) to kilobytes. */
 u32 decode_igd_memory_size(const u32 gms)
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 5114e0bc3e..6170e41a3c 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -4,7 +4,6 @@
 
 #include <cbmem.h>
 #include <commonlib/helpers.h>
-#include <stdint.h>
 #include <arch/romstage.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
@@ -14,6 +13,7 @@
 #include <northbridge/intel/x4x/x4x.h>
 #include <program_loading.h>
 #include <cpu/intel/smm_reloc.h>
+#include <types.h>
 
 /** Decodes used Graphics Mode Select (GMS) to kilobytes. */
 u32 decode_igd_memory_size(const u32 gms)