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authorElyes HAOUAS <ehaouas@noos.fr>2016-10-31 18:55:04 +0100
committerMartin Roth <martinroth@google.com>2016-12-21 00:05:10 +0100
commitf7acdf82cbfaf3e2b2b0db784b822207f1b1d026 (patch)
tree225cf39869d2da449e48d95112f73ff6e375c262 /src/northbridge/intel
parent1b3a6e4b1489af477cfff1b1df4a37ccdb75f20d (diff)
nb/i945/early_init.c: Add FSB800 and 1067 to Egress Port Virtual Channel
Values based on vendor bios and suggested by Arthur Heymans for FSB1067. FSB1067: The ratio 1067/800 is proportional to the ratio of EPBAR32(0x2c) bits: 0x1a / 0x14 ~ 1067/800 EPVC1IST: The ratio is also proportional to FSB ratios: 0x9c / 0xf0 ~ 533/800. Change-Id: Ib90e8ea1b82f2fcc3b5c199cace32a7f0aff4b5c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17198 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/i945/early_init.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 377302a235..8930cb6326 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -232,8 +232,14 @@ static void i945_setup_egress_port(void)
/* Egress Port Virtual Channel 1 Configuration */
reg32 = EPBAR32(0x2c);
reg32 &= 0xffffff00;
+ if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
+ if ((MCHBAR32(CLKCFG) & 7) == 0)
+ reg32 |= 0x1a; /* 1067MHz */
+ }
if ((MCHBAR32(CLKCFG) & 7) == 1)
reg32 |= 0x0d; /* 533MHz */
+ if ((MCHBAR32(CLKCFG) & 7) == 2)
+ reg32 |= 0x14; /* 800MHz */
if ((MCHBAR32(CLKCFG) & 7) == 3)
reg32 |= 0x10; /* 667MHz */
EPBAR32(0x2c) = reg32;
@@ -245,11 +251,23 @@ static void i945_setup_egress_port(void)
reg32 |= (0x0a << 16);
EPBAR32(EPVC1RCAP) = reg32;
+ if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
+ if ((MCHBAR32(CLKCFG) & 7) == 0){ /* 1067MHz */
+ EPBAR32(EPVC1IST + 0) = 0x01380138;
+ EPBAR32(EPVC1IST + 4) = 0x01380138;
+ }
+ }
+
if ((MCHBAR32(CLKCFG) & 7) == 1) { /* 533MHz */
EPBAR32(EPVC1IST + 0) = 0x009c009c;
EPBAR32(EPVC1IST + 4) = 0x009c009c;
}
+ if ((MCHBAR32(CLKCFG) & 7) == 2) { /* 800MHz */
+ EPBAR32(EPVC1IST + 0) = 0x00f000f0;
+ EPBAR32(EPVC1IST + 4) = 0x00f000f0;
+ }
+
if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */
EPBAR32(EPVC1IST + 0) = 0x00c000c0;
EPBAR32(EPVC1IST + 4) = 0x00c000c0;