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authorArthur Heymans <arthur@aheymans.xyz>2017-12-11 07:36:15 +0100
committerArthur Heymans <arthur@aheymans.xyz>2017-12-12 12:05:22 +0000
commitf6f4ba9e4579e2c6ce5bda375c0f3b7cd7595bd7 (patch)
treea4c13164045e468c5cd869a994e17471b606a945 /src/northbridge/intel
parentcda1c4a521918056cfb4f1fc4f6a259e58fe0260 (diff)
nb/intel/x4x/rcven.c: Fix programming coarse offset
This fixes some bitwise logic errors that caused the coarse offset not to be programmed. This fixes a regression introduced by 6d7a8c "nb/intel/x4x/raminit: Rework receive enable calibration" where the coarse offset doesn't get programmed anymore. TESTED on Foxconn g41s-k on a DIMM where the final DQS receive enable delays are close but above and below the edge of a coarse delay setting. Change-Id: I41869815f782a2ea1178bdea006e3a7587441323 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/x4x/rcven.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c
index 23f8d52c3c..cc45aa9331 100644
--- a/src/northbridge/intel/x4x/rcven.c
+++ b/src/northbridge/intel/x4x/rcven.c
@@ -365,8 +365,9 @@ void rcven(const struct sysinfo *s)
"medium: %d; tap: %d\n",
channel, lane, reg8, timing[lane].medium,
timing[lane].tap);
- MCHBAR16(0x400 * channel + 0x5fa) &=
- ~(3 << (lane * 2)) | (reg8 << (lane * 2));
+ MCHBAR16(0x400 * channel + 0x5fa) =
+ (MCHBAR16(0x400 * channel + 0x5fa) &
+ ~(3 << (lane * 2))) | (reg8 << (lane * 2));
}
/* simply use timing[0] to program mincoarse */
timing[0].coarse = mincoarse;