haswell: relocate `romstage_common` to northbridge

Other platforms do this as well. It will ease refactoring on follow-ups.

Change-Id: I643982a58c6f5370c78acef93740f27df001a06d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>

3 files changed, 92 insertions, 0 deletions

diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index 8ef3079f51..b2fd5307bf 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -14,6 +14,7 @@ ramstage-y += minihd.c
 
 romstage-y += memmap.c
 romstage-y += raminit.c
+romstage-y += romstage.c
 romstage-y += early_init.c
 romstage-y += report_platform.c
 
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index c3930493da..b98d88085e 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -189,6 +189,16 @@
 
 void intel_northbridge_haswell_finalize_smm(void);
 
+struct pei_data;
+struct rcba_config_instruction;
+struct romstage_params {
+	struct pei_data *pei_data;
+	const void *gpio_map;
+	const struct rcba_config_instruction *rcba_config;
+	void (*copy_spd)(struct pei_data *peid);
+};
+void romstage_common(const struct romstage_params *params);
+
 void haswell_early_initialization(void);
 void haswell_late_initialization(void);
 void set_translation_table(int start, int end, u64 base, int inc);
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
new file mode 100644
index 0000000000..579eca791b
--- /dev/null
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <cf9_reset.h>
+#include <timestamp.h>
+#include <cpu/x86/lapic.h>
+#include <cbmem.h>
+#include <commonlib/helpers.h>
+#include <romstage_handoff.h>
+#include <cpu/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/lynxpoint/me.h>
+
+void romstage_common(const struct romstage_params *params)
+{
+	int wake_from_s3;
+
+	enable_lapic();
+
+	wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
+
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	haswell_early_initialization();
+	printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
+
+	if (wake_from_s3) {
+#if CONFIG(HAVE_ACPI_RESUME)
+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+#else
+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+		wake_from_s3 = 0;
+#endif
+	}
+
+	/* Prepare USB controller early in S3 resume */
+	if (wake_from_s3)
+		enable_usb_bar();
+
+	post_code(0x3a);
+
+	/* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */
+	params->pei_data->boot_mode = wake_from_s3 ? 2 : 0;
+
+	timestamp_add_now(TS_BEFORE_INITRAM);
+
+	report_platform_info();
+
+	if (params->copy_spd != NULL)
+		params->copy_spd(params->pei_data);
+
+	sdram_initialize(params->pei_data);
+
+	timestamp_add_now(TS_AFTER_INITRAM);
+
+	post_code(0x3b);
+
+	intel_early_me_status();
+
+	if (!wake_from_s3) {
+		cbmem_initialize_empty();
+		/* Save data returned from MRC on non-S3 resumes. */
+		save_mrc_data(params->pei_data);
+	} else if (cbmem_initialize()) {
+	#if CONFIG(HAVE_ACPI_RESUME)
+		/* Failed S3 resume, reset to come up cleanly */
+		system_reset();
+	#endif
+	}
+
+	haswell_unhide_peg();
+
+	setup_sdram_meminfo(params->pei_data);
+
+	romstage_handoff_init(wake_from_s3);
+
+	post_code(0x3f);
+}