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authorElyes HAOUAS <ehaouas@noos.fr>2020-04-23 16:32:27 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-01 06:10:49 +0000
commit2d7173d462c66cbbca6a5354c1ac719941e117d9 (patch)
tree432c8fd4e65f30668e8e4f98d90a092a2a6fccd8 /src/northbridge/intel
parentfdbdca2ec3a3a28142791cd331fcf42da59e9d38 (diff)
src: Remove unused 'include <cpu/x86/cache.h>'
Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40666 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/e7505/raminit.c1
-rw-r--r--src/northbridge/intel/pineview/raminit.c1
-rw-r--r--src/northbridge/intel/x4x/raminit.c1
3 files changed, 0 insertions, 3 deletions
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 8ed5007428..fd88193b91 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -21,7 +21,6 @@
#include <commonlib/helpers.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
#include <assert.h>
#include <spd.h>
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 18e1faa490..aea699e3a8 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -18,7 +18,6 @@
#include <device/pci_ops.h>
#include <commonlib/helpers.h>
#include <console/console.h>
-#include <cpu/x86/cache.h>
#include <delay.h>
#include <lib.h>
#include "pineview.h"
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index f1dc8817e6..797bc5a378 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -17,7 +17,6 @@
#include <cbmem.h>
#include <cf9_reset.h>
#include <console/console.h>
-#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <arch/cpu.h>
#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)