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authorSubrata Banik <subrata.banik@intel.com>2020-09-09 13:34:18 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-09-15 15:13:50 +0000
commit292afef2fbb5eaf46dd3efa0c9a54c125f71ad1a (patch)
tree28db1e208bf70d4b58eed14c9f3d120c217bd0d7 /src/northbridge/intel
parenteb17b475c8be292e6d2b9caa4cef3dd87f21ee42 (diff)
soc/intel/alderlake/romstage: Do initial SoC commit till romstage
List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Add SA EDS document number and chapter number 4. Fill required FSP-M UPD to call FSP-M API Change-Id: I4473aed27363c22e92e66cc6770cb55aae83e75c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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