src/northbridge: Capitalize CPU, RAM and ROM

Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

10 files changed, 12 insertions, 12 deletions

diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c
index 64bf840d3f..5296bdb00e 100644
--- a/src/northbridge/intel/e7501/northbridge.c
+++ b/src/northbridge/intel/e7501/northbridge.c
@@ -69,7 +69,7 @@ static void pci_domain_set_resources(device_t dev)
 			/* Find the limit of the remap window */
 			remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
 		}
-		/* Write the ram configuration registers,
+		/* Write the RAM configuration registers,
 		 * preserving the reserved bits.
 		 */
 		tolm_r = pci_read_config16(mc_dev, 0xc4);
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index 08cd023c92..4a3e99379e 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -65,7 +65,7 @@ static void pci_domain_set_resources(device_t dev)
 			/* Find the limit of the remap window */
 			remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
 		}
-		/* Write the ram configuration registers,
+		/* Write the RAM configuration registers,
 		 * preserving the reserved bits.
 		 */
 		tolm_r = pci_read_config16(mc_dev, TOLM);
diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c
index b24e3a6c06..c987cb3e2c 100644
--- a/src/northbridge/intel/gm45/early_reset.c
+++ b/src/northbridge/intel/gm45/early_reset.c
@@ -64,6 +64,6 @@ void gm45_early_reset(void/*const timings_t *const timings*/)
 
 	/* Perform system reset through CF9 interface. */
 	outb(0x02, 0xcf9); /* Set system reset bit. */
-	outb(0x06, 0xcf9); /* Set cpu reset bit, too. */
+	outb(0x06, 0xcf9); /* Set CPU reset bit, too. */
 	halt();
 }
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 5e592337f2..b15f933c45 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -65,7 +65,7 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE
 	default 0x2000
 	help
 	  The amount of anticipated stack usage from the data cache
-	  during pre-ram rom stage execution.
+	  during pre-ram ROM stage execution.
 
 config HAVE_MRC
 	bool "Add a System Agent binary"
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c
index 10e57f4873..8d37f3859c 100644
--- a/src/northbridge/intel/i3100/northbridge.c
+++ b/src/northbridge/intel/i3100/northbridge.c
@@ -93,7 +93,7 @@ static void pci_domain_set_resources(device_t dev)
 			/* Find the offset of the remap window from tolm */
 			remapoffsetk = remapbasek - tolmk;
 		}
-		/* Write the ram configruation registers,
+		/* Write the RAM configruation registers,
 		 * preserving the reserved bits.
 		 */
 		tolm_r = pci_read_config16(mc_dev, 0xc4);
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index b69efbc4bb..443716f9ce 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -603,7 +603,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 {
 	long dimm_mask;
 
-	/* Test if we can read the spd and if ram is ddr or ddr2 */
+	/* Test if we can read the spd and if RAM is ddr or ddr2 */
 	dimm_mask = spd_detect_dimms(ctrl);
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 		printk(BIOS_ERR, "No memory for this cpu\n");
diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c
index aba19663bb..e9b1cac996 100644
--- a/src/northbridge/intel/i855/northbridge.c
+++ b/src/northbridge/intel/i855/northbridge.c
@@ -87,7 +87,7 @@ static void pci_domain_set_resources(device_t dev)
 			 */
 			tolmk = tomk;
 		}
-		/* Write the ram configuration registers,
+		/* Write the RAM configuration registers,
 		 * preserving the reserved bits.
 		 */
 
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 63ee98b46a..478966308c 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -878,7 +878,7 @@ static void spd_update(u8 reg, u32 new_value)
 #endif
 }
 
-/* if ram still doesn't work do this function */
+/* if RAM still doesn't work do this function */
 static void spd_set_undocumented_registers(void)
 {
 	spd_update(0x74, 0x00000001);
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 59a31deacf..5469059070 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -85,7 +85,7 @@ static __attribute__((noinline)) void do_ram_command(u32 command)
 
 static void ram_read32(u32 offset)
 {
-	PRINTK_DEBUG("   ram read: %08x\n", offset);
+	PRINTK_DEBUG("   RAM read: %08x\n", offset);
 
 	read32((void *)offset);
 }
@@ -1453,7 +1453,7 @@ static struct dimm_size sdram_get_dimm_size(struct sys_info *sysinfo, u16 dimmno
  val_err:
 	die("Bad SPD value\n");
  hw_err:
-	/* If a hardware error occurs the spd rom probably does not exist.
+	/* If a hardware error occurs the spd ROM probably does not exist.
 	 * In this case report that there is no memory
 	 */
 	sz.side1 = 0;
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 4ac7f3d6de..421763c2ba 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -1121,7 +1121,7 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size)
 	gfxstolenbase -= tsegbasedelta;
 	toludbase -= tsegbasedelta;
 
-	// Test if it is possible to reclaim a hole in the ram addressing
+	// Test if it is possible to reclaim a hole in the RAM addressing
 	if (tom - me_uma_size > toludbase) {
 		// Reclaim is possible
 		reclaim = 1;
@@ -4080,7 +4080,7 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot,
 	/* Set scheduler parameters */
 	MCHBAR32(0x4c20) = 0x10100005;
 
-	/* Set cpu specific register */
+	/* Set CPU specific register */
 	set_4f8c();
 
 	/* Clear IO reset bit */