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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-02-19 22:08:51 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-03-03 21:04:12 +0100 |
| commit | e1eef694ea6a055ab5f6dc792847702aced5a2ad (patch) | |
| tree | be441d68917dd12956dba6c67f9ab13b5f239c96 /src/northbridge/intel | |
| parent | 9817a37416468cc8a00990e3f431b8d3634f5fcc (diff) | |
intel/nehalem: Use non-powercycle reset.
Change-Id: Ibc2421a50e272a580461e4eacec6cfcd38654fe8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5266
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/nehalem/raminit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index c967e3979f..46a15a9271 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -3804,7 +3804,7 @@ void chipset_init(const int s3resume) if ((x2ca8 & 1) || (x2ca8 == 8 && !s3resume)) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); write_mchbar8(0x2ca8, 0); - outb(0xe, 0xcf9); + outb(0x6, 0xcf9); #if REAL while (1) { asm volatile ("hlt"); |